DC Field | Value | Language |
---|---|---|
dc.contributor.author | Lee, Joon Yeong | ko |
dc.contributor.author | Yang, Jaehyeok | ko |
dc.contributor.author | Yoon, Jong Hyeok | ko |
dc.contributor.author | Kwon, Soon Won | ko |
dc.contributor.author | Won, Hyosup | ko |
dc.contributor.author | Han, Jinho | ko |
dc.contributor.author | Bae, Hyeon-Min | ko |
dc.date.accessioned | 2016-09-07T04:24:35Z | - |
dc.date.available | 2016-09-07T04:24:35Z | - |
dc.date.created | 2015-11-24 | - |
dc.date.created | 2015-11-24 | - |
dc.date.issued | 2016-06 | - |
dc.identifier.citation | IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, v.24, no.6, pp.2310 - 2320 | - |
dc.identifier.issn | 1063-8210 | - |
dc.identifier.uri | http://hdl.handle.net/10203/212887 | - |
dc.description.abstract | A four-parallel 10-Gb/s referenceless-and-masterless phase rotator-based transceiver is presented. Entire lanes operate independently just like the conventional voltage-controlled-oscillator-based parallel referenceless designs while saving power and area. The measured recovered-clock jitter in each lane is 1.24 ps(rms) and the transceiver surpasses the OC-192 jitter-tolerance specification. The power efficiency of the proposed parallel transceiver fabricated in a 90-nm CMOS process is 6.325 mW/(Gb/s). | - |
dc.language | English | - |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.subject | AUTOMATIC FREQUENCY ACQUISITION | - |
dc.subject | DATA RECOVERY CIRCUIT | - |
dc.subject | NM CMOS | - |
dc.subject | CLOCK | - |
dc.subject | JITTER | - |
dc.subject | NOISE | - |
dc.subject | GAIN | - |
dc.title | A 4 x 10-Gb/s Referenceless-and-Masterless Phase Rotator-Based Parallel Transceiver in 90-nm CMOS | - |
dc.type | Article | - |
dc.identifier.wosid | 000380029700026 | - |
dc.identifier.scopusid | 2-s2.0-84949895235 | - |
dc.type.rims | ART | - |
dc.citation.volume | 24 | - |
dc.citation.issue | 6 | - |
dc.citation.beginningpage | 2310 | - |
dc.citation.endingpage | 2320 | - |
dc.citation.publicationname | IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS | - |
dc.identifier.doi | 10.1109/TVLSI.2015.2502957 | - |
dc.contributor.localauthor | Bae, Hyeon-Min | - |
dc.description.isOpenAccess | N | - |
dc.type.journalArticle | Article | - |
dc.subject.keywordAuthor | Clock and data recovery (CDR) | - |
dc.subject.keywordAuthor | frequency-locked loop (FLL) | - |
dc.subject.keywordAuthor | masterless | - |
dc.subject.keywordAuthor | parallel transceiver | - |
dc.subject.keywordAuthor | phase-locked loop (PLL) | - |
dc.subject.keywordAuthor | referenceless | - |
dc.subject.keywordAuthor | stochastic reference clock generator (SRCG) | - |
dc.subject.keywordPlus | AUTOMATIC FREQUENCY ACQUISITION | - |
dc.subject.keywordPlus | DATA RECOVERY CIRCUIT | - |
dc.subject.keywordPlus | REFERENCE CLOCK | - |
dc.subject.keywordPlus | NM CMOS | - |
dc.subject.keywordPlus | JITTER | - |
dc.subject.keywordPlus | NOISE | - |
dc.subject.keywordPlus | GAIN | - |
dc.subject.keywordPlus | CDR | - |
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