DC Field | Value | Language |
---|---|---|
dc.contributor.author | Lee, Taeho | ko |
dc.contributor.author | Kim, Yonghun | ko |
dc.contributor.author | Sim, Jaehyeong | ko |
dc.contributor.author | Park, Jun-Seok | ko |
dc.contributor.author | Kim, Lee-Sup | ko |
dc.date.accessioned | 2016-07-04T01:55:47Z | - |
dc.date.available | 2016-07-04T01:55:47Z | - |
dc.date.created | 2015-06-12 | - |
dc.date.created | 2015-06-12 | - |
dc.date.issued | 2016-04 | - |
dc.identifier.citation | IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, v.24, no.4, pp.1450 - 1459 | - |
dc.identifier.issn | 1063-8210 | - |
dc.identifier.uri | http://hdl.handle.net/10203/208754 | - |
dc.description.abstract | A digital clock and data recovery (CDR) employing a time-dithered delta-sigma modulator (TDDSM) is presented. By enabling hybrid dithering of a sampling period as well as an output bit of the TDDSM, the proposed CDR enhances the resolution of digitally controlled oscillator, removes a low-pass filter in the integral path, and reduces jitter generation. Fabricated in a 65-nm CMOS process, the proposed CDR operates at 5-Gb/s data rate with BER < 10(-12) for PRBS 31. The CDR consumes 13.32 mW at 5 Gb/s and achieves 2.14 and 29.7 ps of a long-term rms and peak-to-peak jitter, respectively. | - |
dc.language | English | - |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.subject | PHASE-LOCKED LOOP | - |
dc.subject | CHARGE PUMP | - |
dc.subject | CIRCUIT | - |
dc.subject | CMOS | - |
dc.subject | TRACKING | - |
dc.subject | DESIGN | - |
dc.subject | GB/S | - |
dc.title | A 5-Gb/s 2.67-mW/Gb/s Digital Clock and Data Recovery With Hybrid Dithering Using a Time-Dithered Delta-Sigma Modulator | - |
dc.type | Article | - |
dc.identifier.wosid | 000373020200023 | - |
dc.identifier.scopusid | 2-s2.0-84937691408 | - |
dc.type.rims | ART | - |
dc.citation.volume | 24 | - |
dc.citation.issue | 4 | - |
dc.citation.beginningpage | 1450 | - |
dc.citation.endingpage | 1459 | - |
dc.citation.publicationname | IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS | - |
dc.identifier.doi | 10.1109/TVLSI.2015.2449866 | - |
dc.contributor.localauthor | Kim, Lee-Sup | - |
dc.type.journalArticle | Article | - |
dc.subject.keywordAuthor | Delta-sigma modulator (DSM) | - |
dc.subject.keywordAuthor | digital clock and data recovery (CDR) | - |
dc.subject.keywordAuthor | digitally controlled oscillator (DCO) | - |
dc.subject.keywordAuthor | high-speed serial link | - |
dc.subject.keywordAuthor | hybrid dithering | - |
dc.subject.keywordAuthor | loop delay | - |
dc.subject.keywordAuthor | resolution | - |
dc.subject.keywordAuthor | time-dithered DSM (TDDSM) | - |
dc.subject.keywordPlus | PHASE-LOCKED LOOP | - |
dc.subject.keywordPlus | CHARGE PUMP | - |
dc.subject.keywordPlus | CIRCUIT | - |
dc.subject.keywordPlus | CMOS | - |
dc.subject.keywordPlus | TRACKING | - |
dc.subject.keywordPlus | DESIGN | - |
dc.subject.keywordPlus | GB/S | - |
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