DC Field | Value | Language |
---|---|---|
dc.contributor.author | Song, Jinook | ko |
dc.date.accessioned | 2016-04-20T06:21:34Z | - |
dc.date.available | 2016-04-20T06:21:34Z | - |
dc.date.created | 2015-10-29 | - |
dc.date.created | 2015-10-29 | - |
dc.date.issued | 2015-10 | - |
dc.identifier.citation | IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, v.62, no.10, pp.967 - 971 | - |
dc.identifier.issn | 1549-7747 | - |
dc.identifier.uri | http://hdl.handle.net/10203/205281 | - |
dc.description.abstract | This brief presents a new multistage noise-shaping (MASH) structure that has less hardware by applying partially folded architecture. A folded MASH architecture that exploits adders in half is introduced, and the proposed architecture combines the folded MASH architecture and the conventional MASH architecture. The noise power spectrum of the proposed architecture is mathematically analyzed and the noise-shaping capability of the MASH architecture is preserved. | - |
dc.language | English | - |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.title | Hardware Reduction of MASH Delta-Sigma Modulator Based on Partially Folded Architecture | - |
dc.type | Article | - |
dc.identifier.wosid | 000361989700011 | - |
dc.identifier.scopusid | 2-s2.0-84942867113 | - |
dc.type.rims | ART | - |
dc.citation.volume | 62 | - |
dc.citation.issue | 10 | - |
dc.citation.beginningpage | 967 | - |
dc.citation.endingpage | 971 | - |
dc.citation.publicationname | IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS | - |
dc.identifier.doi | 10.1109/TCSII.2015.2458034 | - |
dc.type.journalArticle | Article | - |
dc.subject.keywordAuthor | Delta-sigma modulator (DSM) | - |
dc.subject.keywordAuthor | fractional-N frequency synthesizer | - |
dc.subject.keywordAuthor | multistage noise shaping (MASH) | - |
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