A 1.93 TOPS/W Scalable Deep Learning/Inference Processor with Tetra-parallel MIMD Architecture for Big Data Applications
| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | Yoo, Hoi-Jun | ko |
| dc.contributor.author | Park, Seongwook | ko |
| dc.contributor.author | Bong, Kyeongryeol | ko |
| dc.contributor.author | Shin, Dongjoo | ko |
| dc.contributor.author | Lee, Jinmook | ko |
| dc.contributor.author | Choi, Sungpill | ko |
| dc.date.accessioned | 2016-04-18T05:21:10Z | - |
| dc.date.available | 2016-04-18T05:21:10Z | - |
| dc.date.created | 2015-11-19 | - |
| dc.date.created | 2015-11-19 | - |
| dc.date.issued | 2015-02-23 | - |
| dc.identifier.citation | IEEE International Solid- State Circuits Conference, pp.80 - 81 | - |
| dc.identifier.uri | http://hdl.handle.net/10203/204565 | - |
| dc.language | English | - |
| dc.publisher | IEEE | - |
| dc.title | A 1.93 TOPS/W Scalable Deep Learning/Inference Processor with Tetra-parallel MIMD Architecture for Big Data Applications | - |
| dc.type | Conference | - |
| dc.identifier.scopusid | 2-s2.0-84940782827 | - |
| dc.type.rims | CONF | - |
| dc.citation.beginningpage | 80 | - |
| dc.citation.endingpage | 81 | - |
| dc.citation.publicationname | IEEE International Solid- State Circuits Conference | - |
| dc.identifier.conferencecountry | US | - |
| dc.identifier.conferencelocation | San Francisco Marriott | - |
| dc.contributor.localauthor | Yoo, Hoi-Jun | - |
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