A 21fJ/conv-step 9 ENOB 1.6GS/s 2x Time-Interleaved FATI SAR ADC with Background Offset and Timing-Skew Calibration in 45nm CMOS
| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | Sung, BRS | ko |
| dc.contributor.author | Jo, DS | ko |
| dc.contributor.author | Jang, IH | ko |
| dc.contributor.author | Lee, DS | ko |
| dc.contributor.author | You, YS | ko |
| dc.contributor.author | Lee, YH | ko |
| dc.contributor.author | Park, HJ | ko |
| dc.contributor.author | Ryu, Seung-Tak | ko |
| dc.date.accessioned | 2016-04-18T05:20:32Z | - |
| dc.date.available | 2016-04-18T05:20:32Z | - |
| dc.date.created | 2015-11-24 | - |
| dc.date.created | 2015-11-24 | - |
| dc.date.created | 2015-11-24 | - |
| dc.date.issued | 2015-02-25 | - |
| dc.identifier.citation | International Solid-State Circuits Conference (ISSCC) | - |
| dc.identifier.uri | http://hdl.handle.net/10203/204558 | - |
| dc.language | English | - |
| dc.publisher | IEEE | - |
| dc.title | A 21fJ/conv-step 9 ENOB 1.6GS/s 2x Time-Interleaved FATI SAR ADC with Background Offset and Timing-Skew Calibration in 45nm CMOS | - |
| dc.type | Conference | - |
| dc.identifier.wosid | 000355252700197 | - |
| dc.identifier.scopusid | 2-s2.0-84940762178 | - |
| dc.type.rims | CONF | - |
| dc.citation.publicationname | International Solid-State Circuits Conference (ISSCC) | - |
| dc.identifier.conferencecountry | US | - |
| dc.identifier.conferencelocation | San Francisco Marriott | - |
| dc.contributor.localauthor | Ryu, Seung-Tak | - |
| dc.contributor.nonIdAuthor | Sung, BRS | - |
| dc.contributor.nonIdAuthor | Jo, DS | - |
| dc.contributor.nonIdAuthor | Jang, IH | - |
| dc.contributor.nonIdAuthor | Lee, DS | - |
| dc.contributor.nonIdAuthor | You, YS | - |
| dc.contributor.nonIdAuthor | Lee, YH | - |
| dc.contributor.nonIdAuthor | Park, HJ | - |
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