DC Field | Value | Language |
---|---|---|
dc.contributor.author | Yoon, Taehun | ko |
dc.contributor.author | Lee, Joon Young | ko |
dc.contributor.author | Han, Kwangseok | ko |
dc.contributor.author | Lee, Jeongsup | ko |
dc.contributor.author | Lee, Sangeun | ko |
dc.contributor.author | Kim, Taeho | ko |
dc.contributor.author | Won, Hyo Sup | ko |
dc.contributor.author | Park, Jinho | ko |
dc.contributor.author | Bae, Hyeon-Min | ko |
dc.date.accessioned | 2016-04-18T05:12:31Z | - |
dc.date.available | 2016-04-18T05:12:31Z | - |
dc.date.created | 2015-11-20 | - |
dc.date.created | 2015-11-20 | - |
dc.date.created | 2015-11-20 | - |
dc.date.created | 2015-11-20 | - |
dc.date.issued | 2015-06-18 | - |
dc.identifier.citation | 2015 SYMPOSIUM ON VLSI CIRCUITS, pp.C212 - C213 | - |
dc.identifier.uri | http://hdl.handle.net/10203/204471 | - |
dc.description.abstract | This paper presents the industry's first low-power 100-Gigabit Ethernet (GbE) multi-link gearbox (MLG) IC, which facilitates transport of independent 10-GbE and 40-GbE signals to 4×25G physical layers implementing 100GBASE-R. The IC consumes only 1.37-W while implementing complicated reverse gearbox functionality. The measured TX jitter from the 25-Gb/s lane is 1.6-psrms, and the recovered clock jitter is 0.5-psrms. The measured RX input sensitivity for a BER 10-12 is 42-mVppd. The proposed gearbox IC, fabricated in a 40nm CMOS process, occupies 3.7×3.4-mm2. The power consumption of RX and TX in 25G interfaces are 47-mW and 51-mW, respectively, and those of a 10G interfaces are 24-mW and 25-mW, respectively. Gearbox functionalities are verified with embedded self-test logics. | - |
dc.language | English | - |
dc.publisher | The Japan Society of Applied Physics, The IEEE Solid-State Circuits Society | - |
dc.title | A 100-GbE Reverse Gearbox IC in 40nm CMOS for Supporting Legacy 10-and 40-GbE Standards | - |
dc.type | Conference | - |
dc.identifier.wosid | 000370961400081 | - |
dc.identifier.scopusid | 2-s2.0-84957874268 | - |
dc.type.rims | CONF | - |
dc.citation.beginningpage | C212 | - |
dc.citation.endingpage | C213 | - |
dc.citation.publicationname | 2015 SYMPOSIUM ON VLSI CIRCUITS | - |
dc.identifier.conferencecountry | JA | - |
dc.identifier.conferencelocation | RIHGA Royal Hotel Kyoto | - |
dc.identifier.doi | 10.1109/VLSIC.2015.7231262 | - |
dc.embargo.liftdate | 9999-12-31 | - |
dc.embargo.terms | 9999-12-31 | - |
dc.contributor.localauthor | Bae, Hyeon-Min | - |
dc.contributor.nonIdAuthor | Han, Kwangseok | - |
dc.contributor.nonIdAuthor | Lee, Jeongsup | - |
dc.contributor.nonIdAuthor | Lee, Sangeun | - |
dc.contributor.nonIdAuthor | Kim, Taeho | - |
dc.contributor.nonIdAuthor | Park, Jinho | - |
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