Quasi-Primitive Block-Wise Concatenated BCH Codes With Collaborative Decoding for NAND Flash Memories

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dc.contributor.authorKim, Daesungko
dc.contributor.authorHa, Jeongseokko
dc.date.accessioned2016-04-14T02:59:17Z-
dc.date.available2016-04-14T02:59:17Z-
dc.date.created2015-10-28-
dc.date.created2015-10-28-
dc.date.issued2015-10-
dc.identifier.citationIEEE TRANSACTIONS ON COMMUNICATIONS, v.63, no.10, pp.3482 - 3496-
dc.identifier.issn0090-6778-
dc.identifier.urihttp://hdl.handle.net/10203/203739-
dc.description.abstractIn this work, we propose a novel design rule of blockwise concatenated Bose-Chaudhuri-Hocquenghem (BC-BCH) codes for storage devices using multi-level per cell (MLC) NAND flash memories. BC-BCH codes designed in accordance with the proposed design rule are called quasi-primitive BC-BCH codes in which constituent BCH codes are deliberately chosen for their lengths to be as close to primitive BCH codes as possible. It will be shown that such quasi-primitive BC-BCH codes can achieve significant improvements of error-correcting capability over the existing BC-BCH codes when an iterative hard-decision based decoding (IHDD) is assumed. In addition, we propose a novel collaborative decoding algorithm which targets at resolving dominant error patterns associated with the IHDD. Error-rate performances of error-control systems with the proposed quasi-primitive BC-BCH and existing BC-BCH codes are compared. For more comprehensive performance comparisons, systems with a hypothetically long BCH code and a product code are also considered in the comparisons.-
dc.languageEnglish-
dc.publisherIEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC-
dc.subjectDECISION ERROR-CORRECTION-
dc.subjectPRODUCT CODE-
dc.subjectLDPC-
dc.subjectARCHITECTURE-
dc.subjectSCHEMES-
dc.subjectPOWER-
dc.subjectCMOS-
dc.subjectVLSI-
dc.titleQuasi-Primitive Block-Wise Concatenated BCH Codes With Collaborative Decoding for NAND Flash Memories-
dc.typeArticle-
dc.identifier.wosid000363257200004-
dc.identifier.scopusid2-s2.0-84958156299-
dc.type.rimsART-
dc.citation.volume63-
dc.citation.issue10-
dc.citation.beginningpage3482-
dc.citation.endingpage3496-
dc.citation.publicationnameIEEE TRANSACTIONS ON COMMUNICATIONS-
dc.contributor.localauthorHa, Jeongseok-
dc.type.journalArticleArticle-
dc.subject.keywordAuthorChannel coding-
dc.subject.keywordAuthorerror correction codes-
dc.subject.keywordAuthordecoding-
dc.subject.keywordAuthorflash memories-
dc.subject.keywordPlusDECISION ERROR-CORRECTION-
dc.subject.keywordPlusPRODUCT CODE-
dc.subject.keywordPlusLDPC-
dc.subject.keywordPlusARCHITECTURE-
dc.subject.keywordPlusSCHEMES-
dc.subject.keywordPlusPOWER-
dc.subject.keywordPlusCMOS-
dc.subject.keywordPlusVLSI-
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