DC Field | Value | Language |
---|---|---|
dc.contributor.author | Kim, Daesung | ko |
dc.contributor.author | Ha, Jeongseok | ko |
dc.date.accessioned | 2016-04-14T02:59:17Z | - |
dc.date.available | 2016-04-14T02:59:17Z | - |
dc.date.created | 2015-10-28 | - |
dc.date.created | 2015-10-28 | - |
dc.date.issued | 2015-10 | - |
dc.identifier.citation | IEEE TRANSACTIONS ON COMMUNICATIONS, v.63, no.10, pp.3482 - 3496 | - |
dc.identifier.issn | 0090-6778 | - |
dc.identifier.uri | http://hdl.handle.net/10203/203739 | - |
dc.description.abstract | In this work, we propose a novel design rule of blockwise concatenated Bose-Chaudhuri-Hocquenghem (BC-BCH) codes for storage devices using multi-level per cell (MLC) NAND flash memories. BC-BCH codes designed in accordance with the proposed design rule are called quasi-primitive BC-BCH codes in which constituent BCH codes are deliberately chosen for their lengths to be as close to primitive BCH codes as possible. It will be shown that such quasi-primitive BC-BCH codes can achieve significant improvements of error-correcting capability over the existing BC-BCH codes when an iterative hard-decision based decoding (IHDD) is assumed. In addition, we propose a novel collaborative decoding algorithm which targets at resolving dominant error patterns associated with the IHDD. Error-rate performances of error-control systems with the proposed quasi-primitive BC-BCH and existing BC-BCH codes are compared. For more comprehensive performance comparisons, systems with a hypothetically long BCH code and a product code are also considered in the comparisons. | - |
dc.language | English | - |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.subject | DECISION ERROR-CORRECTION | - |
dc.subject | PRODUCT CODE | - |
dc.subject | LDPC | - |
dc.subject | ARCHITECTURE | - |
dc.subject | SCHEMES | - |
dc.subject | POWER | - |
dc.subject | CMOS | - |
dc.subject | VLSI | - |
dc.title | Quasi-Primitive Block-Wise Concatenated BCH Codes With Collaborative Decoding for NAND Flash Memories | - |
dc.type | Article | - |
dc.identifier.wosid | 000363257200004 | - |
dc.identifier.scopusid | 2-s2.0-84958156299 | - |
dc.type.rims | ART | - |
dc.citation.volume | 63 | - |
dc.citation.issue | 10 | - |
dc.citation.beginningpage | 3482 | - |
dc.citation.endingpage | 3496 | - |
dc.citation.publicationname | IEEE TRANSACTIONS ON COMMUNICATIONS | - |
dc.contributor.localauthor | Ha, Jeongseok | - |
dc.type.journalArticle | Article | - |
dc.subject.keywordAuthor | Channel coding | - |
dc.subject.keywordAuthor | error correction codes | - |
dc.subject.keywordAuthor | decoding | - |
dc.subject.keywordAuthor | flash memories | - |
dc.subject.keywordPlus | DECISION ERROR-CORRECTION | - |
dc.subject.keywordPlus | PRODUCT CODE | - |
dc.subject.keywordPlus | LDPC | - |
dc.subject.keywordPlus | ARCHITECTURE | - |
dc.subject.keywordPlus | SCHEMES | - |
dc.subject.keywordPlus | POWER | - |
dc.subject.keywordPlus | CMOS | - |
dc.subject.keywordPlus | VLSI | - |
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