DC Field | Value | Language |
---|---|---|
dc.contributor.author | Hur, Jae | ko |
dc.contributor.author | Choi, Ji-Min | ko |
dc.contributor.author | Woo, Jong-Ho | ko |
dc.contributor.author | Jang, Hyunjae | ko |
dc.contributor.author | Choi, Yang-Kyu | ko |
dc.date.accessioned | 2016-04-12T07:54:54Z | - |
dc.date.available | 2016-04-12T07:54:54Z | - |
dc.date.created | 2015-06-21 | - |
dc.date.created | 2015-06-21 | - |
dc.date.created | 2015-06-21 | - |
dc.date.issued | 2015-09 | - |
dc.identifier.citation | IEEE TRANSACTIONS ON ELECTRON DEVICES, v.62, no.9, pp.2710 - 2716 | - |
dc.identifier.issn | 0018-9383 | - |
dc.identifier.uri | http://hdl.handle.net/10203/203407 | - |
dc.description.abstract | A general potential model is proposed for all types of double-gate junctionless FETs (DGJL-FETs), i.e., the symmetric versus asymmetric DG structures and the tied versus untied DG structures. The potential model is obtained with a simple form through a 2-D Poisson's equation based on the assumption that the vertical channel potential is approximated to a cubic function of the position in order to consider all types of DGJL-FETs. An analytical threshold voltage (VT) equation via the potential model is derived with the gate voltage when the sum of the depletion widths from the front-gate and the back-gate equals the body thickness. The analytic solution of VT shows good agreement with the simulation results down to a channel length <20 nm. The variability of VT is analyzed for various device parameters. The back-gate effect of the untied DG structure is also investigated. | - |
dc.language | English | - |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.subject | MOSFETS | - |
dc.subject | TRANSISTORS | - |
dc.title | A Generalized Threshold Voltage Model of Tied and Untied Double-Gate Junctionless FETs for a Symmetric and Asymmetric Structure | - |
dc.type | Article | - |
dc.identifier.wosid | 000360401500002 | - |
dc.identifier.scopusid | 2-s2.0-85027938176 | - |
dc.type.rims | ART | - |
dc.citation.volume | 62 | - |
dc.citation.issue | 9 | - |
dc.citation.beginningpage | 2710 | - |
dc.citation.endingpage | 2716 | - |
dc.citation.publicationname | IEEE TRANSACTIONS ON ELECTRON DEVICES | - |
dc.identifier.doi | 10.1109/TED.2015.2436415 | - |
dc.contributor.localauthor | Choi, Yang-Kyu | - |
dc.contributor.nonIdAuthor | Woo, Jong-Ho | - |
dc.contributor.nonIdAuthor | Jang, Hyunjae | - |
dc.type.journalArticle | Article | - |
dc.subject.keywordAuthor | Asymmetric double-gate (DG) | - |
dc.subject.keywordAuthor | DG junctionless FET (DGJL-FET) | - |
dc.subject.keywordAuthor | generalized threshold voltage (V-T) model | - |
dc.subject.keywordAuthor | symmetric DG | - |
dc.subject.keywordAuthor | tied mode DG | - |
dc.subject.keywordAuthor | untied mode DG | - |
dc.subject.keywordPlus | MOSFETS | - |
dc.subject.keywordPlus | TRANSISTORS | - |
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