Showing results 1 to 49 of 49
A Complete Model for Glitch Analysis in Logic Circuits Taewhan Kim, IEEE International ASIC/SOC Conference (ASIC), 2000 |
A low phase noise microwave oscillator using split ring resonators Jung J.; Cho C.S.; Lee J.W.; Kim J.; Kim T.H., 36th European Microwave Conference, EuMC 2006, pp.95 - 98, 2006-09-10 |
A Methodology for Verifying Memory Access Protocols in Behavioral Synthesis Taewhan Kim, IEEE International Conference on Computer-Aided Design (ICCAD), 2000 |
A Non-Zero Delay Model for Glitch Analysis in Logic Circuits Taewhan Kim, IEEE MidWest Symposium on Circuits and Systems (MWSCAS), 2000 |
A Scheduling Algorithm for Conditional Resource Sharing Taewhan Kim, IEEE International Conference on Computer-Aided Design (ICCAD), pp.84 - 87, 1991 |
A Stepwise Refinement Data Path Synthesis Procedure for Easy Testability Taewhan Kim, IEEE European Design and Test Conference (EDAC), pp.586 - 590, 1994 |
A Timing-Driven Synthesis of Arithmetic Circuits using Carry-Save-Adders Taewhan Kim, IEEE Asia and South Pacific Design Automation Conference (ASP-DAC), pp.313 - 316, 2000 |
A Verification of Memory Access Protocols in Behavioral Synthesis Taewhan Kim, IEEE MidWest Symposium on Circuits and Systems (MWSCAS), 2000 |
Address assignment combined with scheduling in DSP code generation Choi Y.; Kim T., 39th Annual Design Automation Conference, DAC'02, pp.225 - 230, 2002-06-10 |
Address code generation utilizing memory sharing in DSP processors Kim T.; Hong S., 2005 IEEE International 48th Midwest Symposium on Circuits and Systems, MWSCAS 2005, v.2005, pp.579 - 582, 2005-08-07 |
An Accurate Design Exploration of Arithmetic Circuits using Carry-Save-Adder Cells Taewhan Kim, IEEE Asia and South Pacific Design Automation Conference (ASP-DAC), pp.622 - 627, 2001 |
An Efficient Binding Algorithm for Power Optimization based on Network Flow Method Taewhan Kim, 6th Korea-Japan Joint Workshop on Algorithms and Computation, pp.9 - 14, 2001 |
An Efficient Data Path Synthesis Algorithm for Behavioral-level Power Optimization Taewhan Kim, IEEE International Symposium on Circuits and Systems (ISCAS), pp.I-294 - I-297, 1999 |
An Efficient Inverse Multiplier/Divider Architecture for Cryptography Systems Taewhan Kim, IEEE International Symposium on Circuits and Systems (ISCAS), 2003 |
An Integrated Approach to Data Path Synthesis for Low Power Taewhan Kim, IEEE International ASIC/SOC Conference (ASIC), pp.125 - 129, 1999 |
An Integrated Data Path Synthesis Algorithm based on Network Flow Method Taewhan Kim, IEEE Custom Integrated Circuits Conference (CICC), pp.615 - 618, 1995 |
Arithmetic Optimization using Carry-Save Adders Taewhan Kim, ACM/IEEE Design Automation Conference (DAC), pp.442 - 447, 1998 |
Behavioral-Level Partitioning for Low Power Design in Control-Dominated Applications Taewhan Kim, ACM Great Lakes Symposium on VLSI (GLSVLSI), pp.156 - 161, 2000 |
Coupling-aware high-level interconnect synthesis for low power Lyuh C.-G.; Kim T.; Kim K.-W., IEEE/ACM International Conference on Computer Aided Design (ICCAD), pp.609 - 613, 2002-11-10 |
DSP 내장형 시스템 설계에서 코드 스케쥴링을 이용한 주소 코드 최적화 김태환, 한국정보고학회 학술 대회, pp.7 - 9, 2002 |
Enhanced Bus Invert Encoding for Low-Power Taewhan Kim, IEEE International SYmposium on Circuits and Systems, 2002 |
G-Vector: A New Model for Glitch Analysis Taewhan Kim, IEEE International ASIC/SOC Conference (ASIC), pp.159 - 162, 1999 |
Memory access driven storage assignment for variables in embedded system design Choi Y.; Kim T., Proceedings of the ASP - DAC 2004 Asia and South Pacific Design Automation Conference - 2004, pp.478 - 481, 2004-01-27 |
Memory Layout Technique for Variables Utilizing Efficient DRAM Access Modes in Embedded System Design Taewhan Kim, IEEE/ACM Design Automation Conference (DAC), pp.881 - 886, 2003 |
Optimal allocation of carry-save-adders in arithmetic optimization Um Junhyung; Kim Taewhan; Liu C.L., Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design (ICCAD-99), pp.410 - 413, 1999-11-07 |
Optimal integration of inter-task and intra-task dynamic voltage scaling techniques for hard real-time applications Seo J.; Kim T.; Dutt N.D., ICCAD-2005: IEEE/ACM International Conference on Computer-Aided Design, 2005, v.2005, pp.449 - 454, 2005-11-06 |
Optimal Voltage Allocation Techniques for Dynamically Variable Voltage Processors Taewhan Kim, IEEE/ACM Design Automation Conference (DAC), pp.125 - 130, 2003 |
Power Optimization in VLSI Design based on Efficient Network Flow Computations Taewhan Kim, 6th Korea-Japan Workshop on ALgorithms and Computation, pp.3 - 8, 2001 |
Practical Issues on Behavioral Synthesis 김태환, CAD 및 VLSI 설계 연구회 학술발표회 대회, pp.1 - 4, 1999 |
Profile-based optimal intra-task voltage scheduling for hard real-time applications Seo J.; Kim T.; Chung K.-S., Proceedings of the 41st Design Automation Conference, pp.87 - 92, 2004-06-07 |
Register Allocation for Dataflow Graphs with Conditional Branches and Loops Taewhan Kim, IEEE European Design Automation Conference (Euro-DAC), pp.232 - 237, 1993 |
Resource-constrained low-power bus encoding with crosstalk delay elimination Cha M.; Lyuh C.-G.; Kim T., Proceedings of the ASP - DAC 2004 Asia and South Pacific Design Automation Conference - 2004, pp.835 - 838, 2004-01-27 |
Utilization of Carry-Save Adders in Arithmetic Optimization Taewhan Kim, IEEE International ASIC/SOC Conference (ASIC), pp.173 - 177, 1999 |
Utilization of Multiport Memories in Data Path Synthesis Taewhan Kim, ACM/IEEE Design Automation Conference (DAC), pp.298 - 302, 1993 |
Wallace-Tree based Timing-Driven Synthesis of Arithmetic Circuits Taewhan Kim, IEEE International Conference on VLSI and CAD (VLSICAD), pp.89 - 94, 1999 |
WFA를 이용한 이미지 압축 알고리즘에 대한 분석 김태환, 한국정보과학회 학술 대회, pp.727 - 729, 2002 |
고속 회로를 위한 비트 단위의 연산 최적화 김태환, 한국정보과학회 학술 대회, pp.21 - 23, 2000 |
내장형 시스템에서의 암호 연산을 위한 효율적인 역원 연산기와 나눗셈 연산기의 구현 김태환, 한국정보과학회 컴퓨터시스템연구회 학술대회 논문지(A), 2002 |
네트워크 플로우에 기반한 아키텍쳐 수준에서의 전력 최적화 김태환, 한국정보과학회 학술 대회, pp.667 - 669, 2002 |
분산된 VLIW 구조에서의 최대전력 최소화 방법 김태환, SOC Design Conference, 2002 |
상위 단계에서의 스케쥴링 효과를 이용한 메모리 탐색 김태환; 서재원, 한국정보과학회 학술 대회, pp.3 - 5, 2002 |
스마트 카드에서의 Multiplicative Inverse연산을 위한 효율적인 하드웨어의 구현 김태환, 한국정보처리학회 학술대회 논문지(A), 2002 |
연산회로 최적화를 위한 배선의 재배열 김태환; 엄준형, 한국정보과학회 학술 대회, pp.661 - 663, 2002 |
저전력 소모를 위한 상위 수준의 효과적인 바인딩 알고리즘 김태환, 한국정보과학회 학술 대회, pp.19 - 21, 2002 |
저전력 회로 설계를 위한 분할 버스-인버트 코딩 기법 김태환, 한국정보과학회 학술대회, pp.27 - 29, 2000 |
저전력 회로를 위한 비트단위의 연산 최적화 김태환, 한국정보과학회 학술대회, pp.16 - 19, 2002 |
최종 배선을 고려한 연산회로 합성 김태환, 한국정보과학회 학술대회, pp.664 - 667, 2002 |
캐리-세이브 가신기를 이용한 지연시간 최적화를 위한 연산기 합성 김태환, 한국정보과학회 학술 대회, pp.18 - 20, 2000 |
회로 속도 최소화를 위한 캐리-세이브 가산기 모델링 및 실험 김태환, 한국 반도체 학술 대회 (KCS), 1999 |
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