Browse "RIMS Conference Papers" by Author Taewhan Kim
Showing results 1 to 28 of 28
| A Complete Model for Glitch Analysis in Logic Circuits Taewhan Kim, IEEE International ASIC/SOC Conference (ASIC), 2000 |
| A Methodology for Verifying Memory Access Protocols in Behavioral Synthesis Taewhan Kim, IEEE International Conference on Computer-Aided Design (ICCAD), 2000 |
| A Non-Zero Delay Model for Glitch Analysis in Logic Circuits Taewhan Kim, IEEE MidWest Symposium on Circuits and Systems (MWSCAS), 2000 |
| A Scheduling Algorithm for Conditional Resource Sharing Taewhan Kim, IEEE International Conference on Computer-Aided Design (ICCAD), pp.84 - 87, 1991 |
| A Stepwise Refinement Data Path Synthesis Procedure for Easy Testability Taewhan Kim, IEEE European Design and Test Conference (EDAC), pp.586 - 590, 1994 |
| A Timing-Driven Synthesis of Arithmetic Circuits using Carry-Save-Adders Taewhan Kim, IEEE Asia and South Pacific Design Automation Conference (ASP-DAC), pp.313 - 316, 2000 |
| A Verification of Memory Access Protocols in Behavioral Synthesis Taewhan Kim, IEEE MidWest Symposium on Circuits and Systems (MWSCAS), 2000 |
| Address Code Optimization using Code Scheduling for Digital Signal Processors Taewhan Kim, IEEE International Symposium on Circuits and Systems, IEEE, 2002-05 |
| An Accurate Design Exploration of Arithmetic Circuits using Carry-Save-Adder Cells Taewhan Kim, IEEE Asia and South Pacific Design Automation Conference (ASP-DAC), pp.622 - 627, 2001 |
| An Efficient Binding Algorithm for Power Optimization based on Network Flow Method Taewhan Kim, 6th Korea-Japan Joint Workshop on Algorithms and Computation, pp.9 - 14, 2001 |
| An Efficient Data Path Synthesis Algorithm for Behavioral-level Power Optimization Taewhan Kim, IEEE International Symposium on Circuits and Systems (ISCAS), pp.I-294 - I-297, 1999 |
| An Efficient Inverse Multiplier/Divider Architecture for Cryptography Systems Taewhan Kim, IEEE International Symposium on Circuits and Systems (ISCAS), 2003 |
| An Efficient Low-Power Binding Algorithm in High-Level Synthesis Taewhan Kim, IEEE International Symposium on Circuits and Systems, IEEE, 2002-05 |
| An Integrated Approach to Data Path Synthesis for Low Power Taewhan Kim, IEEE International ASIC/SOC Conference (ASIC), pp.125 - 129, 1999 |
| An Integrated Data Path Synthesis Algorithm based on Network Flow Method Taewhan Kim, IEEE Custom Integrated Circuits Conference (CICC), pp.615 - 618, 1995 |
| Arithmetic Optimization using Carry-Save Adders Taewhan Kim, ACM/IEEE Design Automation Conference (DAC), pp.442 - 447, 1998 |
| Behavioral-Level Partitioning for Low Power Design in Control-Dominated Applications Taewhan Kim, ACM Great Lakes Symposium on VLSI (GLSVLSI), pp.156 - 161, 2000 |
| Enhanced Bus Invert Encoding for Low-Power Taewhan Kim, IEEE International SYmposium on Circuits and Systems, 2002 |
| G-Vector: A New Model for Glitch Analysis Taewhan Kim, IEEE International ASIC/SOC Conference (ASIC), pp.159 - 162, 1999 |
| Low Power Bus Encoding with Crosstalk Delay Elimination Taewhan Kim, IEEE ASIC/SOC Conference (ASIC), IEEE, 2002-09 |
| Memory Exploration utilizing Scheduling Effects in High-level Synthesis Taewhan Kim, IEEE International Symposium on Circuits and Systems, IEEE, 2002-05 |
| Memory Layout Technique for Variables Utilizing Efficient DRAM Access Modes in Embedded System Design Taewhan Kim, IEEE/ACM Design Automation Conference (DAC), pp.881 - 886, 2003 |
| Optimal Voltage Allocation Techniques for Dynamically Variable Voltage Processors Taewhan Kim, IEEE/ACM Design Automation Conference (DAC), pp.125 - 130, 2003 |
| Power Optimization in VLSI Design based on Efficient Network Flow Computations Taewhan Kim, 6th Korea-Japan Workshop on ALgorithms and Computation, pp.3 - 8, 2001 |
| Register Allocation for Dataflow Graphs with Conditional Branches and Loops Taewhan Kim, IEEE European Design Automation Conference (Euro-DAC), pp.232 - 237, 1993 |
| Utilization of Carry-Save Adders in Arithmetic Optimization Taewhan Kim, IEEE International ASIC/SOC Conference (ASIC), pp.173 - 177, 1999 |
| Utilization of Multiport Memories in Data Path Synthesis Taewhan Kim, ACM/IEEE Design Automation Conference (DAC), pp.298 - 302, 1993 |
| Wallace-Tree based Timing-Driven Synthesis of Arithmetic Circuits Taewhan Kim, IEEE International Conference on VLSI and CAD (VLSICAD), pp.89 - 94, 1999 |
Discover
Type
- 3,515 Conference
Date issued
- 324 2020 - 2023
- 961 2010 - 2019
- 1,104 2000 - 2009
- 918 1990 - 1999
- 155 1980 - 1989