Browse "RIMS Conference Papers" by Author 997
Showing results 1 to 43 of 43
| 1.8-GHz self-calibrated phase-locked loop with precise I/Q matching Park Chan-Hong; Kim Ook; Kim Beomsup, 2000 Symposium on VLSI Circuits, pp.242 - 243, 2000-06-15 |
| A 13 bit 2.5 MHz Self-Calibrated Pipelined A/D Converter in 3um CMOS Beom-Sup Kim, IEEE Symposium on VLSI CIrcuits, pp.33 - 34, 1990 |
| A 250MHz direct digital frequency synthesizer with ΣΔ noise shaping Song Y.; Kim B., 2003 Digest of Technical Papers, 2003-02-09 |
| A 250MHz Low Jitter Adaptive Bandwidth PLL Beom-Sup Kim, IEEE International Solid-State Circuit Conferece, 1999 |
| A 30MHz High-Speed Analog/Digital PLL in 2um CMOS Beom-Sup Kim, IEEE Int. Conf. on Solid-State Circuits, pp.104 - 105, 1990 |
| A 5-GHz Band I/Q Generator using a Self-Calibration Technique Beom-Sup Kim; Hyung-Cheol Shin, European Solid-State Circuit Conference, pp.807 - 810, 2002 |
| A 500Mb/s/pin quadruple data rate SDRAM interface using a Skew cancellation technique Kim J.; Wang S.-H.; Lee J.; Hyoung Sik Nam; Young Gon Kim; Jae Hoon Shim; Hyung Ki Ahn; et al, 2000 IEEE International Solid-State Circuits Conference 47th Annual ISSCC, pp.404 - 405, 2000-02-07 |
| A 640 MB/s Bi-Directional Data Strobed, Double-Data-Rate SDRAM with a 40mW DLL Circuit for a 256MB Memory System Beom-Sup Kim, IEEE International Solid State Circuits Conference, 1998 |
| A Digital Audio Signal Processor for Cellular Phone Application Beom-Sup Kim, ASP-DAC, pp.183 - 187, 1995 |
| A Digital Phase-Locked Loop with Loop Gains Derived from RLS Method Beom-Sup Kim, IEEE International Conf. on Communications, pp.11 - 15, 1997 |
| A fully Integerated Low Noise RF Frequncy Synthesizer Design for Mobile Communication Application Beom-Sup Kim, IEEE Symposium on VLSI Circuits, pp.56 - 57, 1996 |
| A fully integrated CMOS RF front-end with on-chip VCO for WCDMA applications Lim K.; Park C.-H.; Hyung Ki Ahn; Jae Joon Kim; Kim B., Digest of Technical Papers - IEEE International Solid-State Circuits Conference, pp.286 - 287, 2001-02-05 |
| A High Speed Digital Data Separator Design Using Real Time DSP for DISK Drive Applications Beom-Sup Kim, IEEE International Symposium on Circuit and Systems, 1992 |
| A Low Jitter Digital Timing Synchronizer for CAP-based VDSL System Beom-Sup Kim, ESSCIRC 2001, pp.168 - 171, 2001 |
| A Low Jitter Mixed DLL for High Speed DRAMs Beom-Sup Kim, IEEE European Solid-State Circuits Conference, 1999 |
| A low power CMOS bluetooth transceiver with a digital offset canceling DLL-based GFSK demodulator Park C.-H.; Byun S.; Song Y.; Wang S.; Conroy C.; Kim B., 2003 Digest of Technical Papers, 2003-02-09 |
| A low-noise, 900-MHz VCO in 0.6-μm CMOS Park Chan-Hong; Kim Beomsup, Proceedings of the 1998 Symposium on VLSI Circuits, pp.28 - 29, 1998-06-11 |
| A low-phase-noise CMOS LC oscillator with a ring structure Jae Joon Kim; Kim B., 2000 IEEE International Solid-State Circuits Conference 47th Annual ISSCC, pp.430 - 431, 2000-02-07 |
| A quad-channel 3.125Gb/s/ch serial-link transceiver with mixed-mode adaptive equalizer in 0.18um CMOS Yang J.; Kim J.; Byun S.; Conroy C.; Kim B., Digest of Technical Papers - IEEE International Solid-State Circuits Conference: Visuals Supplement, v.47, pp.134 -, 2003-02-15 |
| A quad-channel 3.125Gb/s/ch serial-link transceiver with mixed-mode adaptive equalizer in 0.18um CMOS Yang J.; Kim J.; Byun S.; Conroy C.; Kim B., Digest of Technical Papers - 2004 IEEE International Solid-State Circuits Conference, v.47, pp.176 -, 2003-02-15 |
| A third-order ΣΔ modulator in 0.18μm CMOS with calibrated mixed-mode integrators Shim J.H.; Kim B., 2004 Symposium on VLSI Circuits, Digest of Technical Papers, 2004 VLSI, pp.78 - 81, 2004-06-17 |
| Adaptive Carrier Recovery System Design for IS54 Digital Mobile Communication Application 김범섭, 국내외 한국과학기술자 학술회의 추계 웍크샵, pp.155 - 157, 1994 |
| Adaptive Carrier Recovery Using Dual Loop DPLL for Mobile Communication Applications Beom-Sup Kim, IEEE Int. Conf. on Communication, pp.1757 - 1761, 1993 |
| All CMOS Analog Pulse Detection System for Data Storage Applicaions Beom-Sup Kim, IEEE International Symposium on Circuit and Systems, 1992 |
| An area-efficient implementation of digital-IF QAM coherent demodulator for software-defined radio receivers Song Y.; Kim J.; Kim B., 2004 Symposium on VLSI Circuits, Digest of Technical Papers, 2004 VLSI, pp.160 - 163, 2004-06-17 |
| Analysis of Timing Jitter in CMOS Ring Oscillators Beom-Sup Kim, IEEE International Symposium on Circuit and Systems, pp.27 - 30, 1994 |
| Bandwidth Lim Kyoohyun; Park Chan-Hong; Kim Beomsup, Proceedings of the 1998 IEEE International Symposium on Circuits and Systems, ISCAS. Part 5 (of 6), v.1, pp.163 - 166, 1998-05-31 |
| Baseband clock recovery algorithm for pi/4-QPSK modulated signals Lee Jeong Eun; Choi Seung Hee; Kim Beomsup, Proceedings of the 47th IEEE Vehicular Technology Conference. Part 1 (of 3), 1997, v.3, pp.1729 - 1733, 1997-05-04 |
| Digital audio signal processor for cellular phone application Yang Jeongsik; Park Chanhong; Kim Beomsup, Proceedings of the 1995 Asia and South Pacific Design Automation Conference, ASP-DAC'95, pp.183 - 187, 1995-08-29 |
| Digital Carrier Recovery with Adaptive Dual Loop DPLL for Mobile Communication Applications Beom-Sup Kim, IEEE International Conference on Acoustics, Speech & Signal Processing, pp.29 - 32, 1993 |
| Digital phase-locked loop with variable loop gains derived from RLS method Chun Byungjin; Choi Seung Hee; Kim Beomsup, Proceedings of the 1997 IEEE International Conference on Communications, ICC. Part 3 (of 3), v.1, pp.11 - 15, 1997-06-08 |
| Low Jitter Digital Timing Synchronizer for CAP-based VDSL System Beom-Sup Kim, European Solid-State Circuits Conference, pp.146 - 147, 2001 |
| Low Noise Clock Synthesizer Design Using Optimal Bandwidth Beom-Sup Kim, IEEE International Symposium on Circuits and Systems, 1998 |
| Low power Circuit Design Issues 김범섭, 저전압, 저전력 VLSI Workshop, 1995 |
| Low Power CMOS on Chip Voltage Reference Using MOS PTAT Beom-Sup Kim, IEEE International ASIC conference, pp.316 - 320, 1997 |
| MIGHTI : A High Performance 16-bit DSP for Mobile Communication Applications Beom-Sup Kim, European Solid-State Circuits Conference (ESSCIRC '98), 1998 |
| MIxed-Mode Synchronization in Digital Communication 김범섭, CAD 및 VLSI, 1996 |
| Optimal MMSE Gear-Shifting Algorithm for the Fast Synchronization of DPLL Beom-Sup Kim, IEEE International Symposium on Circuit and Systems, pp.172 - 175, 1993 |
| PLL/DLL system noise analysis for low jitter clock synthesizer design Kim Beomsup; Weigandt Todd C.; Gray Paul R., Proceedings of the 1994 IEEE International Symposium on Circuits and Systems. Part 3 (of 6), v.4, pp.31 - 34, 1994-05-30 |
| Skew에 둔감한 광대역 입출력용 Delay Locked Loop 김범섭, CAD 및 VLSI, 1998 |
| The Research on the Effective Algorithm for Device Simulation 김범섭, KIEE Semiconductor and CAD Research Conference, pp.19 - 22, 1985 |
| 저전력 칩상 전압 안정기 설계 김범섭, 대한전자공학회 학술발표회, 1996 |
| 칩상 튜닝회로를 포함한 3.0V 연속시간 저대역 필터의 설계 김범섭, CAD 및 VLSI, 1996 |
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