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| NO | Title, Author(s) (Publication Title, Volume Issue, Page, Issue Date) |
|---|---|
| A 1.8-GHz self-calibrated phase-locked loop with precise I/Q matching Park, CH; Kim, O; Kim, Beom-Sup, IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.36, no.5, pp.777 - 783, 2001-05 | |
| Digital calibration techniques for pipelined ADCs Kim, J; Song, Y; Kim, Beom-Sup, IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, v.E87A, pp.3433 - 3435, 2004-12 | |
| A Low-Power CMOS Bluetooth RF Transceiver with a Digital Offset Canceling DLL-Based GFSK Demodulator s. byun; c.-h. park; y. song; s. wang; c. s. g. conroy; Kim, Beom-Sup, IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.38, no.10, pp.1609 - 1618, 2003-10 | |
| A fully integrated CMOS RF front-end with on-chip VCO for W-CDMA applications Ahn, HK; Lim, K; Park, CH; Kim, JJ; Kim, Beom-Sup, IEICE TRANSACTIONS ON ELECTRONICS, v.E87C, no.6, pp.1047 - 1053, 2004 | |
| A 500-Mb/a quadruple data rate SDRAM interface using a skew cancellation technique Wang, SH; Kim, J; Lee, J; Nam, HS; Kim, YG; Shim, JH; Ahn, HK; Kang, S; Jeong, BH; Ahn, JH; Kim, Beom-Sup, IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.36, no.4, pp.648 - 657, 2001-04 | |
| A DLL-based frequency synthesizer with selective reuse of a delay cell scheme for 2.4 GHz ISM band Kang, S; Kim, Beom-Sup, IEICE TRANSACTIONS ON ELECTRONICS, v.E88C, no.1, pp.149 - 153, 2005 | |
| Optimal loop bandwidth design for low noise PLL applications Lim, K; Choi, SH; Kim, Beom-Sup, IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, v.E80A, no.10, pp.1979 - 1985, 1997-10 | |
| A novel high-speed ring oscillator for multiphase clock generation using negative skewed delay scheme Lee, Seog-Jun; Kim, Beom-Sup; Lee, Kwyro, IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.32, no.2, pp.289 - 291, 1997-02 | |
| Dual-loop digital PLL design for adaptive clock recovery Kim, TH; Kim, Beom-Sup, IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, v.E81A, no.12, pp.2509 - 2514, 1998-12 | |
| A 64-Mbit, 640-MByte/s bidirectional data strobed, double-data-rate SDRAM with a 40-mW DLL for a 256-MByte memory system Kim, CH; Lee, J; Kim, Beom-Sup; Park, CS; Lee, S; Park, CW; Roh, JG; Nam, HS; Kim, DG; Jung, TS; Cho, SI, IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.33, no.11, pp.1703 - 1710, 1998-11 |
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