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Results 1-6 of 6 (Search time: 0.004 seconds).
| NO | Title, Author(s) (Publication Title, Volume Issue, Page, Issue Date) |
|---|---|
| Register allocation - A hierarchical reduction approach Chaeryung Park; Kim, Taewhan; C.L. Liu, JOURNAL OF VLSI SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY, v.19, no.3, pp.269 - 285, 1998 | |
| A New Approach to the Multiport Memory Allocation Problem in Data Path Synthesis Taewhan Kim; C.L. Liu, INTEGRATION-THE VLSI JOURNAL, v.19, no.3, pp.133 - 160, 1995-10 | |
| Domino Logic Synthesis based on Implication Graph for Set of Mandatory Assignments Ki-Wook Kim; Taewhan Kim; C.L. Liu; Sung-Mo Kang, IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, v.21, no.2, pp.232 - 240, 2002-02 | |
| A Scheduling Algorithm for Conditional Resource Sharing - A Hierarchical Reduction Approach Taewhan Kim; Noritake Yonezawa; Jane W.S. Liu; C.L. Liu, IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, v.13, no.4, pp.425 - 438, 1994-04 | |
| An Integrated Approach to Data Path Synthesis for Behavioral-level Power Optimization Chaeryung Park; Taewhan Kim; C.L. Liu, VLSI DESIGN, v.11, no.4, pp.381 - 396, 2000 | |
| An Integrated Algorithm for Incremental Data Path Synthesis Taewhan Kim; C.L. Liu, JOURNAL OF VLSI SIGNAL PROCESSING, v.12, no.3, pp.265 - 285, 1996-06 |