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NO | Title, Author(s) (Publication Title, Volume Issue, Page, Issue Date) |
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Coupling-aware high-level interconnect synthesis Lyuh, CG; Kim, Taewhan; Kim, KW, IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, v.23, no.1, pp.157 - 164, 2004-01 | |
Ontimal intratask dynamic voltage-scaling technique and its practical extensions Seo, J; Kim, Taewhan; Lee, Joonwon, IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, v.25, no.1, pp.47 - 57, 2006-01 | |
Memory allocation and mapping in high-level synthesis - An integrated approach Seo, J; Kim, Taewhan; Panda, PR, IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, v.11, no.5, pp.928 - 938, 2003-10 |
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