Browse "RIMS Journal Papers" by Subject DPLL
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| A Low-Noise, Fast-Lock Phase-Locked Loop with Adaptive Bandwidth Control joonsuk lee; Kim, Beom-Sup, IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.35, no.8, pp.1137 - 1145, 2000-08 |
| Dual-loop digital PLL design for adaptive clock recovery Kim, TH; Kim, Beom-Sup, IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, v.E81A, no.12, pp.2509 - 2514, 1998-12 |
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