Browse "School of Electrical Engineering(전기및전자공학부)" by Author Chung, K.
Showing results 1 to 16 of 16
| A 116fps 74mW mobile heterogeneous 3D-Media processor for 3D display contents Kim, S.-H.; Kim, H.-Y.; Kim, Y.-J.; Chung, K.; Kim, D.; Kim, Lee-Sup, 2009 Symposium on VLSI Circuits, pp.258 - 259, 2009-06-16 |
| A 120Mvertices/s multi-threaded VLIW vertex processor for mobile multimedia applications Yu, C.-H.; Chung, K.; Kim, D.; Kim, Lee-Sup, 2006 IEEE International Solid-State Circuits Conference, ISSCC, 2006-02-06 |
| A 186Mvertices/s 161mW floating-point vertex processor for mobile graphics systems Yu, C.-H.; Chung, K.; Kim, D.; Kim, Lee-Sup, 2007 IEEE Custom Integrated Circuits Conference, CICC, pp.579 - 582, 2007-09-16 |
| A 3-way SIMD engine for programmable triangle setup in embedded 3D graphics hardware Chung, K.; Kim, D.; Kim, Lee-Sup, IEEE International Symposium on Circuits and Systems 2005, ISCAS 2005, pp.4546 - 4549, IEEE, 2005-05-23 |
| A 36fps SXGA 3D display processor with a programmable 3D graphics rendering engine Kim, S.-H.; Yoon, J.-S.; Yu, C.-H.; Kim, D.; Chung, K.; Lim, H.S.; Park, HyunWook; et al, 54th IEEE International Solid-State Circuits Conference, ISSCC 2007, pp.276 - 277, IEEE, 2007-02-11 |
| A graphics and vision unified processor with 0.89uw/fps pose estimation engine for augmented reality Yoon, J.-S.; Kim, J.-H.; Kim, H.-E.; Lee, W.-Y.; Kim, S.-H.; Chung, K.; Park, J.-S.; et al, 2010 IEEE International Solid-State Circuits Conference, ISSCC 2010, pp.336 - 337, IEEE, 2010-02-07 |
| A hardware-like high-level language based environment for 3D graphics architecture exploration Lee, I.; Kim, J.-Y.; Im, Y.-H.; Choi, Y.; Shin, H.; Han, C.; Kim, D.; et al, Proceedings of the 2003 IEEE International Symposium on Circuits and Systems, IEEE, 2003-05-25 |
| A PN triangle generation unit for fast and simple tessellation hardware Chung, K.; Kim, Lee-Sup, Proceedings of the 2003 IEEE International Symposium on Circuits and Systems, pp.II-728 - II-731, IEEE, 2003-05-25 |
| A tessellator based on a vertex shader for bandwidth-efficient mobile 3D graphics Chung, K.; Yu, C.-H.; K, D; Kim, Lee-Sup, 2008 International SoC Design Conference, ISOCC 2008, 2008-11-24 |
| An SoC with 1.3Gtexels/s 3D graphics full pipeline engine for consumer applications Kim, D.; Chung, K.; Yu, C.-H.; Kim, C.-H.; Lee, I.; Bae, J.; Kim, Y.-J.; et al, 2005 IEEE International Solid-State Circuits Conference, ISSCC, v.48, pp.144 -, IEEE, 2005-02-06 |
| Area-efficient special function unit for mobile vertex processors Chung, K.; Kim, Lee-Sup, ELECTRONICS LETTERS, v.45, no.16, pp.826 - 33, 2009-07 |
| Bank-partition and multi-fetch scheme for floating-point special function units in multi-core systems Kim, Y.-J.; Chung, K.; Kim, Lee-Sup; Seong, M.P., IEEE International Symposium on Circuits and Systems, ISCAS 2009, pp.1803 - 1806, 123, 2009-05-24 |
| Clipping-ratio-independent 3D graphics clipping engine by dual-thread algorithm Kim, J.-H.; Chung, K.; Kim, Y.-J.; Kim, S.-H.; Kim, Lee-Sup, 2008 IEEE International Symposium on Circuits and Systems, ISCAS 2008, pp.3534 - 3537, 2008-05-18 |
| Memory bandwidth saving by hardware tessellation with vertex shader Chung, K.; Yu, C. -H.; Kim, D.; Kim, Lee-Sup, ELECTRONICS LETTERS, v.45, no.5, pp.259 - 260, 2009-02 |
| Tessellation-enabled shader for a bandwidth-limited 3D graphics engine Chung, K.; Yu, C.-H.; Kim, D.; Kim, Lee-Sup, IEEE 2008 Custom Integrated Circuits Conference, CICC 2008, pp.367 - 370, 2008-09-21 |
| Vertex cache of programmable geometry processor for mobile multimedia application Chung, K.; Yu, C.-H.; Kim, Lee-Sup, ISCAS 2006: 2006 IEEE International Symposium on Circuits and Systems, pp.1908 - 1911, IEEE, 2006-05-21 |
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