Browse "School of Electrical Engineering(전기및전자공학부)" by Author 984
Showing results 1 to 60 of 68
| 150 MHz Two Stage Pipeline 32 bit x 32 bit Parallel Multiplier/Accumulator Kim, Lee-Sup; Kitagaki, K; Araki, Y; Oto, T, japan IEICE Spring Conference Proceedings, C-572, pp.5 - 193, 1992 |
| 200 MHz Video-Compression Macrocells Using Low-Swing Diferential Logic with Sense-Amplifying Flip-Flops Kim, Lee-Sup; Matsui, M; Hara, H; Seta, K; Uetani, Y; Nagamatsu, T; Shimazawa, T, Digest of Technical Papers of International Solid-State Circuist Conference, pp.76 - 77, 1994 |
| A 10-Phase 270MHz 5000ppm spread spectrum clock generator Lee, W.-Y.; Kim, Lee-Sup, 2008 International SoC Design Conference, ISOCC 2008, 2008-11-24 |
| A 116fps 74mW mobile heterogeneous 3D-Media processor for 3D display contents Kim, S.-H.; Kim, H.-Y.; Kim, Y.-J.; Chung, K.; Kim, D.; Kim, Lee-Sup, 2009 Symposium on VLSI Circuits, pp.258 - 259, 2009-06-16 |
| A 120Mvertices/s multi-threaded VLIW vertex processor for mobile multimedia applications Yu, C.-H.; Chung, K.; Kim, D.; Kim, Lee-Sup, 2006 IEEE International Solid-State Circuits Conference, ISSCC, 2006-02-06 |
| A 186Mvertices/s 161mW floating-point vertex processor for mobile graphics systems Yu, C.-H.; Chung, K.; Kim, D.; Kim, Lee-Sup, 2007 IEEE Custom Integrated Circuits Conference, CICC, pp.579 - 582, 2007-09-16 |
| A 20Gb/s 1:4 DEMUX without inductors in 0.13um CMOS Kim, B.-G.; Kim, Lee-Sup; Byun, S.; Yu, H.-K., 2006 IEEE International Solid-State Circuits Conference, ISSCC, ISSCC, 2006-02-06 |
| A 250MHz - 2GHz wide range delay-locked loop Kim, B.-G.; Kim, Lee-Sup, Proceedings of the IEEE 2004 Custom Integrated Circuits Conference, CICC, pp.139 - 142, 2004-10-03 |
| A 250MHz Low Voltage Swing Bus Driver for Embedded Memory Logic Kim, Lee-Sup; Lee, HS; Kim, BS; Chang, SH, European Solid-State Circuits Conference, pp.424 - 427, 1999 |
| A 250MHz-2GHz Wide Range Delay-Locked Loop Kim, BG; Kim, Lee-Sup, IEEE Custom Integrated Circuits Conference, pp.139 - 142, IEEE, 2004-10-03 |
| A 275mW heterogeneous multimedia processor for IC-stacking on Si-interposer Kim, H.-E.; Yoon, J.-S.; Hwang, K.-D.; Kim, Y.-J.; Park, J.-S.; Kim, Lee-Sup, 2011 IEEE International Solid-State Circuits Conference, ISSCC 2011, pp.128 - 129, IEEE, 2011-02-20 |
| A 3.2-Gb/s transceiver with a quarter-rate linear phase detector reducing the phase offset Ha, K.-S.; Kim, Lee-Sup, 2008 IEEE Asian Solid-State Circuits Conference, A-SSCC 2008, pp.217 - 220, 2008-11-03 |
| A 36fps SXGA 3D display processor with a programmable 3D graphics rendering engine Kim, S.-H.; Yoon, J.-S.; Yu, C.-H.; Kim, D.; Chung, K.; Lim, H.S.; Park, HyunWook; et al, 54th IEEE International Solid-State Circuits Conference, ISSCC 2007, pp.276 - 277, IEEE, 2007-02-11 |
| A 3D graphics processor with fast 4D vector inner product units and power aware texture cache Yoon, J.-S.; Kim, D.; Yu, C.-H.; Kim, Lee-Sup, IEEE 2008 Custom Integrated Circuits Conference, CICC 2008, pp.539 - 542, 2008-09-21 |
| A 5-Gb/s/pin transceiver for DDR memory interface with a crosstalk suppression scheme Oh, K.-I.; Kim, Lee-Sup; Park, K.-I.; Jun, Y.-H.; Kim, K., IEEE 2008 Custom Integrated Circuits Conference, CICC 2008, pp.639 - 642, 2008-09-21 |
| A 6Gb/s/pin pseudo-differential signaling using common-mode noise rejection techniques without reference signal for DRAM interfaces Ha, K.-S.; Kim, Lee-Sup; Bae, S.-J.; Park, K.-I.; Choi, J.S.; Jun, Y.-H.; Kim, K., 2009 IEEE International Solid-State Circuits Conference ISSCC 2009, pp.138 - 139, 2009-02-08 |
| A 7.4 Gb/s Forwarded Clock Receiver Based on First-Harmonic Injection-Locked Oscillator Using AC Coupled Clock Multiplication Unit in 0.13 um CMOS Kim, Lee-Sup, IEEE CICC 2011, IEEE, 2011 |
| A Clock Delayed Sleep Mode Domino Logic for Wide Dynamic OR Gate Oh, K.-I.; Kim, Lee-Sup, Proceedings of the 2003 International Symposium on Low Power Electronics and Design, (ISLPED'03), pp.176 - 179, 2003-08-25 |
| A Clock Embedded Differential Signaling (CEDS) for the Next Generation TFT-LCD Applications Kim, Lee-Sup; Jeon, HK; Moon, YW; Seo, JI; Na, JH; Oh, HS; Han, DK; et al, SID Symposium 2009, 2009 |
| A Clock-Embedded Voltage Differential Signaling (CVDS) for Chip-On-Glass Application of TFT-LCDs Kim, Lee-Sup, SID Symposium 2010, SID Symposium 2010, 2010 |
| A data pattern-tolerant adaptive equalizer using spectrum balancing method Joo, H.-Y.; Ha, K.-S.; Kim, Lee-Sup, 2009 Symposium on VLSI Circuits, pp.220 - 221, 2009-06-16 |
| A Design of Crosstalk Compensation Circuit in TFT-LCDs Kim, Lee-Sup; Jeong, YC; Soh, HS, Degest of SID 96 , San Diego, pp.259 - 262, 1996 |
| A Direct Digital Frequency Synthesizer Using A New ROM Compression Method Kim, Lee-Sup; Yang, BD, ESSCIRC 2001, 2001 |
| A DLL with jitter-reduction techniques for DRAM interfaces Kim, B.-G.; Kim, Lee-Sup; Park, K.-I.; Jun, Y.-H.; Cho, S.-I., 54th IEEE International Solid-State Circuits Conference, ISSCC 2007, pp.496 -, 2007-02-11 |
| A graphics and vision unified processor with 0.89uw/fps pose estimation engine for augmented reality Yoon, J.-S.; Kim, J.-H.; Kim, H.-E.; Lee, W.-Y.; Kim, S.-H.; Chung, K.; Park, J.-S.; et al, 2010 IEEE International Solid-State Circuits Conference, ISSCC 2010, pp.336 - 337, IEEE, 2010-02-07 |
| A high-speed pattern decoder in MPEG-4 padding block hardware accelerator Mo, H.-C.; Kim, J.-S.; Kim, Lee-Sup, IEEE International Symposium on Circuits and Systems (ISCAS 2001), v.2, IEEE, 2001-05-06 |
| A Low Power 100MHg All digital Delay-Locked Loop Kim, Lee-Sup; Kim, BS, International Symposium on Circuits and Systems, Hong Kong, pp.1820 - 1823, 1997 |
| A low power carry select adder with reduced area Kim, Y.; Kim, Lee-Sup, Thermoelectric Materials 2000-The Next Generation Materials for Small-Scale Refrigeration and Power Generation Applications, v.626, 2000-04-24 |
| A LOW POWER CARRY SELECT ADDER WITH REDUCED AREA Kim, Y; Kim, Lee-Sup, 2001 IEEE International Symposium on Circuits and Systems, pp.218 - 221, IEEE, 2001-05-06 |
| A low power charge recycling ROM architecture Kim, Lee-Sup; Yang, BD, ISCAS 2001, 2001 |
| A low power charge-recycling ROM architecture Yang, B.-D.; Kim, Lee-Sup, Thermoelectric Materials 2000-The Next Generation Materials for Small-Scale Refrigeration and Power Generation Applications, v.626, 2000-04-24 |
| A Low Power ROM using Charge Recycling and Charge Sharing Kim, Lee-Sup, ISSCC 2002, 2002 |
| A Low-Power Quadtree Fractal Image Decoder Kim, Lee-Sup; Kim, CH; Park, HJ, European Solid-State Circuits Conference, pp.414 - 417, 1999 |
| A low-power ROM using charge recycling and charge sharing Yang, B.-D.; Kim, Lee-Sup, 2002 IEEE International Solid-State Circuits Conference, pp.108 -, 2002-02-03 |
| A Mode-Changeable 2-D DCT/IDCT Processor for Digital VCR Kim, Lee-Sup; Paek, SK; Kim, JH; Kwon, BS; Chung, DH, IEEE Consumer Electronics Conference, pp.280 - 281, 1996 |
| A NOR-type High Speed Dual-Modulus Prescaler Kim, Lee-Sup; Sung, KH, ICSPAT, 2000 |
| A Pipelined Row Address Decoding Scheme for Hierarchical Word Line Structure DRAM Kim, Lee-Sup; Hong, YM; Jun, YH, International Conference on VLSI and CAD, pp.259 - 262, 1999 |
| A tessellator based on a vertex shader for bandwidth-efficient mobile 3D graphics Chung, K.; Yu, C.-H.; K, D; Kim, Lee-Sup, 2008 International SoC Design Conference, ISOCC 2008, 2008-11-24 |
| Adaptive selection of an index in a texture cache Kim, C.-H.; Kim, Lee-Sup, IEEE International Conference on Computer Design: VLSI in Computers and Processors, ICCD 2004, pp.295 - 300, 2004-10-11 |
| Advanced contrast enhancement using partially overlapped sub-block histogram equalization Kim, JY; Kim, Lee-Sup; Hwang, SH, Proceedings of the IEEE 2000 Internaitonal Symposium on Circuits and Systems, v.4, 2000-05-28 |
| An 8Gb/s Forwarded-Clock I/O Receiver with up to 1GHz Constant Jitter Tracking Bandwidth Using a Weak Injection-Locked Oscillator in 0.13μm CMOS Kim, Lee-Sup, IEEE Symposium on VLSI Circuits, IEEE, 2011 |
| An Advenced Contrast Enhancement Using Partially Overlapped Sub-Block Histogram Equalizaion Kim, JY; Kim, Lee-Sup; Hwang, SH, IEEE International Symposium on Circuits and Systems, pp.537 - 540, IEEE, 2000-05-28 |
| An area efficient asynchronous gated ring oscillator TDC with minimum GRO stages Hwang, K.-D.; Kim, Lee-Sup, 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems, ISCAS 2010, pp.3973 - 3976, IEEE, 2010-05-30 |
| An ASIC implementation of RCM alogrithms for Synthetic Radar Signal Processing Kim, Lee-Sup; Kim, JH, Proceedings of IEEE Workshop on VLSI Signal Processing, pp.135 - 144, 1995 |
| An SOC with 1.3 Gtexels/sec 3D Graphics Full Pipeline Engine for Consumer Applications Kim, Lee-Sup; Kim, D, ISSCC 2005, 2005 |
| An SoC with 1.3Gtexels/s 3D graphics full pipeline engine for consumer applications Kim, D.; Chung, K.; Yu, C.-H.; Kim, C.-H.; Lee, I.; Bae, J.; Kim, Y.-J.; et al, 2005 IEEE International Solid-State Circuits Conference, ISSCC, v.48, pp.144 -, IEEE, 2005-02-06 |
| ASIC implementation of range cell migration compensation algorithm for synthetic aperture radar signal processing Kim, JH; Kim, Lee-Sup, Proceedings of the 1995 IEEE Workshop on VLSI Signal Processing, pp.135 - 144, 1995-10-16 |
| Case Study:Testing of IP-based Mixed-Signal Fax/Modem System-on-Chip Kim, Lee-Sup; Chang, S; Hwang, SH, Design, Automation and Test in Europe Conference and Exhibition, pp.229 - 233, 2000 |
| Clipping-ratio-independent 3D graphics clipping engine by dual-thread algorithm Kim, J.-H.; Chung, K.; Kim, Y.-J.; Kim, S.-H.; Kim, Lee-Sup, 2008 IEEE International Symposium on Circuits and Systems, ISCAS 2008, pp.3534 - 3537, 2008-05-18 |
| Division-free rasterizer for perspective-correct texture filtering Kim, D.; Kim, Lee-Sup, 2004 IEEE International Symposium on Cirquits and Systems - Proceedings, v.2, 2004-05-23 |
| High speed serial interface for mobile LCD driver IC Jeon, H.-K.; Kim, H.-R.; Choi, J.-M.; Hong, J.-P.; Kim, Y.-S.; Oh, H.-S.; Han, D.-K.; et al, 2008 IEEE International Symposium on Circuits and Systems, ISCAS 2008, pp.157 - 160, 2008-05-18 |
| High Speed, Energy Efficient Master-Slave Flip-Flops Kim, Lee-Sup; Kim, CH, International Conference on VLSI and CAD, pp.537 - 540, 1999 |
| High-data-rate DCT/IDCT architecture by parallel processing Kim, Lee-Sup; Kim, Jae Kyoon; Kim, TY, Proceedings of SPIE, Visual Communications and Image Processing, pp.895 - 905, 1994 |
| High-Speed and Low-Swing On-Chip Bus Interface Using Threshold Voltage Swing Driver and Dual Sensing Amplifie Receiver Kim, Lee-Sup; Yang, BD, European Solid State Circuit Conference, 2000 |
| IRAM Design for Multimedia Applications Kim, Lee-Sup; Kim, BS, Workshop on Mixing Logic and DRAM: Chips that compute and remember, Denver, 1997 |
| Label-free CMOS DNA quantification with on-chip noise reduction schemes Kim, S.-J.; Shenoi, M.; Yoo, K.; Shim, J.; Chung, W.; Ko, C.; Kim, Lee-Sup; et al, 4th International Conference on Solid-State Sensors, Actuators and Microsystems, TRANSDUCERS and EUROSENSORS '07, pp.947 - 950, 2007-06-10 |
| Low power 100 MHz all digital delay-locked loop Kim, BS; Kim, Lee-Sup, Proceedings of the 1997 IEEE International Symposium on Circuits and Systems, ISCAS'97. Part 4 (of 4), v.3, pp.1820 - 1823, 1997-06-09 |
| Metastability of CMOS Latch/Flip-Flop Kim, Lee-Sup; Cline, Ron; Dutton, Robert, IEEE Custom Integated Circuitys Conference Proceedings, pp.26.3/1 - 26.3/4, IEEE, 1989-05-15 |
| Minimized hardware architecture of fast Phong shader using Taylor series approximation in 3D graphics Shin, HC; Lee, JA; Kim, Lee-Sup, Proceedings of the 1998 IEEE International Conference on Computer Design, pp.286 - 291, 1998-10-05 |
| Mode-changeable 2-D DCT/IDCT processor for digital VCR Paek, SK; Kim, JH; Kwon, BS; Chung, DH; Kim, Lee-Sup, Proceedings of the 1996 IEEE International Conference on Consumer Electronics, pp.280 - 281, 1996-06-05 |
Discover
Open Access
- 573 OA Article
Date issued
- 4,871 2020 - 2024
- 18,943 2010 - 2019
- 15,019 2000 - 2009
- 7,644 1990 - 1999
- 2,391 1980 - 1989