Showing results 1 to 3 of 3
A 2.74-pJ/bit, 17.7-Gb/s Iterative Concatenated-BCH Decoder in 65-nm CMOS for NAND Flash Memory Lee, Youngjoo; Yoo, Hoyoung; Jung, Jaehwan; Jo, Jihyuck; Park, In-Cheol, IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.48, no.10, pp.2531 - 2540, 2013-10 |
CMOS THz-ID: A 1.6-mm² Package-Less Identification Tag Using Asymmetric Cryptography and 260-GHz Far-Field Backscatter Communication Khan, Muhammad Ibrahim Wasiq; Ibrahim, Mohamed I.; Juvekar, Chiraag S.; Jung, Wanyeong; Yazicigil, Rabia Tugce; Chandrakasan, Anantha P.; Han, Ruonan, IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.56, no.2, pp.340 - 354, 2021-02 |
Energy-Efficient Symmetric BC-BCH Decoder Architecture for Mobile Storages Hwang, Seokha; Moon, Seungsik; Jung, Jaehwan; Kim, Daesung; Park, In-Cheol; Ha, Jeongseok; Lee, Youngjoo, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS-I: REGULAR PAPERS, v.66, no.11, pp.4462 - 4475, 2019-11 |
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