1 | Assessing the Performance of Novel Two-Dimensional Materials Transistors: First-Principles Based Approach Kim, Bokyeom; Seo, Junbeom; Shin, Mincheol, IEEE TRANSACTIONS ON ELECTRON DEVICES, v.67, no.2, pp.463 - 468, 2020-02 |
2 | Ballistic quantum transport in nanoscale Schottky-barrier tunnel transistors Ahn, C; Shin, Mincheol, IEEE TRANSACTIONS ON NANOTECHNOLOGY, v.5, no.3, pp.278 - 283, 2006-05 |
3 | Effects of Si/SiO2 interface stress on the performance of ultra-thin-body field effect transistors: A first-principles study Jung, Hyo Eun; Shin, Mincheol, NANOTECHNOLOGY, v.29, no.2, 2018-01 |
4 | Efficient Atomistic Simulation of Heterostucture Field-Effect Transistors![open access](/image/layout/oa_logo.png) Ahn, Yongsoo; Shin, Mincheol, IEEE JOURNAL OF THE ELECTRON DEVICES SOCIETY, v.7, no.1, pp.668 - 676, 2019-08 |
5 | First-Principles-Based Quantum Transport Simulations of Interfacial Point Defect Effects on InAs Nanowire Tunnel FETs Lee, Hyeongu; Cho, Yucheol; Jeon, Seonghyeok; Shin, Mincheol, IEEE TRANSACTIONS ON ELECTRON DEVICES, v.68, no.11, pp.5901 - 5907, 2021-11 |
6 | Multi-Space Excitation as an Alternative to the Landauer Picture for Nonequilibrium Quantum Transport![open access](/image/layout/oa_logo.png) Lee, Juho; Kim, Han Seul; Kim, Yong-Hoon, ADVANCED SCIENCE, v.7, no.16, pp.2001038, 2020-08 |
7 | Observation of electron diffraction due to a reflection grating in an electron wave transistor Park, KW; Lee, S; Shin, Mincheol; Yuk, JS; Lee, EH; Kwon, HC, SUPERLATTICES AND MICROSTRUCTURES, v.25, no.1-2, pp.153 - 156, 1999 |
8 | Performance Boost of Si TFETs by Insertion of III-V Dipole Formation Layer: A First Principle Study Lim, Yeongjun; Seo, Junbeom; Shin, Mincheol, IEEE TRANSACTIONS ON ELECTRON DEVICES, v.70, no.6, pp.2956 - 2961, 2023-06 |
9 | Quantum mechanical simulation of hole transport in p-type Si nanowire schottky barrier MOSFETs = P형 실리콘 나노와이어 쇼트키 배리어 트랜지스터에서의 양자 수송 시뮬레이션link Choi, Won-Chul; 최원철; et al, 한국과학기술원, 2011 |
10 | Quantum mechanical simulation of hole transport in p-type Si nanowire schottky barrier MOSFETs = P형 실리콘 나노와이어 쇼트키 배리어 트랜지스터에서의 양자 수송 시뮬레이션link Choi, Won-Chul; 최원철; et al, 한국과학기술원, 2011 |
11 | Quantum simulation of device characteristics of silicon nanowire FETs Shin, Mincheol, IEEE TRANSACTIONS ON NANOTECHNOLOGY, v.6, no.2, pp.230 - 237, 2007-03 |
12 | Quantum Simulation Study on Performance Optimization of GaSb/InAs nanowire Tunneling FET Hur, Ji-Hyun; Jeon, Sanghun, JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, v.16, no.5, pp.630 - 634, 2016-10 |
13 | Surface-Roughness-Limited Mean Free Path in Silicon Nanowire Field Effect Transistors Jung, Hyo-Eun; Shin, Mincheol, IEEE TRANSACTIONS ON ELECTRON DEVICES, v.60, no.6, pp.1861 - 1866, 2013-06 |
14 | Theoretical study of the surface roughness scattering effects on silicon nanowire FETs = 실리콘 나노와이어 트랜지스터에서의 표면 거칠기 충돌영향에 대한 이론연구link Jung, Hyo-Eun; 정효은; et al, 한국과학기술원, 2013 |