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Showing results 1 to 6 of 6

1
Chip-Package Hierarchical Power Distribution Network Modeling and Analysis Based on a Segmentation Method

Kim, Jae-Min; Lee, Woo-Jin; Shim, Yu-Jeong; Shim, Jong-Joo; Kim, Ki-Yeong; Pak, Jun-So; Kim, Joung-Ho, IEEE TRANSACTIONS ON ADVANCED PACKAGING, v.33, no.3, pp.647 - 659, 2010-08

2
Design and analysis of high bandwidth memory (HBM) interposer considering signal and power integrity (SI/PI) for terabyte/s bandwidth system = 테라 바이트 대역폭 시스템을 위한 신호 및 전원 무 결성이 고려된 고 대역폭 메모리 인터포저 설계와 분석link

Cho, Kyungjun; 조경준; et al, 한국과학기술원, 2016

3
Fast and analytical eye diagram estimation method for high bandwidth memory (HBM) channel including Tx power noise and channel crosstalk = 고 대역폭 메모리 채널에서 송신단 전력 노이즈와 채널 간섭 현상을 고려한 빠르고 분석적인 아이다이어그램 예측 기법link

Kim, Ki Yeong; 김기영; et al, 한국과학기술원, 2015

4
Modeling and Analysis of a Power Distribution Network in TSV-Based 3-D Memory IC Including P/G TSVs, On-Chip Decoupling Capacitors, and Silicon Substrate Effects

Kim, Ki-Yeong; Hwang, Chul-Soon; Koo, Kyoung-Choul; Cho, Jong-Hyun; Kim, Hee-Gon; Kim, Joung-Ho; Lee, Jun-Ho; et al, IEEE TRANSACTIONS ON COMPONENTS PACKAGING AND MANUFACTURING TECHNOLOGY, v.2, no.12, pp.2057 - 2070, 2012-12

5
Modeling and measurement of interlevel electromagnetic coupling and fringing effect in a hierarchical power distribution network using segmentation method with resonant cavity model

Kim, Jae-Min; Jeong, You-Chul; Lee, Jun-Ho; Ryu, Chung-Hyun; Shim, Jong-Joo; Shin, Min-Chul; Kim, Joung-Ho, IEEE TRANSACTIONS ON ADVANCED PACKAGING, v.31, pp.544 - 557, 2008-08

6
PDN Impedance Modeling and Analysis of 3D TSV IC by Using Proposed P/G TSV Array Model Based on Separated P/G TSV and Chip-PDN Models

Pak, Jun-So; Kim, Joo-Hee; Cho, Jong-Hyun; Kim, Ki-Yeong; Song, Tai-Gon; Ahn, Seung-Young; Lee, Jun-Ho; et al, IEEE TRANSACTIONS ON COMPONENTS PACKAGING AND MANUFACTURING TECHNOLOGY, v.1, no.2, pp.208 - 219, 2011-02

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