Browse "School of Electrical Engineering(전기및전자공학부)" by Subject ACCELERATOR
Showing results 1 to 10 of 10
| A 0.82 mu W CIS-Based Action Recognition SoC With Self-Adjustable Frame Resolution for Always-on IoT Devices Ryu, Junha; Park, Gwangtae; Im, Dongseok; Kim, Ji-Hoon; Yoo, Hoi-Jun, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, v.68, no.5, pp.1700 - 1704, 2021-05 |
Advanced AI Hardware Designs Based on FPGAs Kim, Joo-Young, ELECTRONICS, v.10, no.20, 2021-10 |
| An Overview of Sparsity Exploitation in CNNs for On-Device Intelligence With Software-Hardware Cross-Layer Optimizations Kang, Sanghoon; Park, Gwangtae; Kim, Sangjin; Kim, Soyeon; Han, Donghyeon; Yoo, Hoi-Jun, IEEE JOURNAL ON EMERGING AND SELECTED TOPICS IN CIRCUITS AND SYSTEMS, v.11, no.4, pp.634 - 648, 2021-12 |
| An SRAM-Based Hybrid Computation-in-Memory Macro Using Current-Reused Differential CCO Choi, Injun; Choi, Edward Jongyoon; Yi, Donghyeon; Jung, Yoontae; Seong, Hoyong; Jeon, Hyuntak; Kweon, Soon-Jae; et al, IEEE JOURNAL ON EMERGING AND SELECTED TOPICS IN CIRCUITS AND SYSTEMS, v.12, no.2, pp.536 - 546, 2022-06 |
| Design of Processing-in-Memory With Triple Computational Path and Sparsity Handling for Energy-Efficient DNN Training Han, Wontak; Heo, Jaehoon; Kim, Junsoo; Lim, Sukbin; Kim, Joo-Young, IEEE JOURNAL ON EMERGING AND SELECTED TOPICS IN CIRCUITS AND SYSTEMS, v.12, no.2, pp.354 - 366, 2022-06 |
| FlashMAC: A Time-Frequency Hybrid MAC Architecture With Variable Latency-Aware Scheduling for TinyML Systems Gweon, Surin; Kang, Sanghoon; Kim, Kwantae; Yoo, Hoi-Jun, IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.57, no.10, pp.2944 - 2956, 2022-10 |
| HNPU: An Adaptive DNN Training Processor Utilizing Stochastic Dynamic Fixed-Point and Active Bit-Precision Searching Han, Donghyeon; Im, Dongseok; Park, Gwangtae; Kim, Youngwoo; Song, Seokchan; Lee, Juhyoung; Yoo, Hoi-Jun, IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.56, no.9, pp.2858 - 2869, 2021-09 |
| Real-Time SSDLite Object Detection on FPGA Suchang Kim; Na, Seungho; Kong, Byeong Yong; Choi, Jae Woong; Park, In-Cheol, IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, v.29, no.6, pp.1192 - 1205, 2021-06 |
| SNPU: An Energy-Efficient Spike Domain Deep-Neural-Network Processor With Two-Step Spike Encoding and Shift-and-Accumulation Unit Kim, Sangyeob; Kim, Sangjin; Um, Soyeon; Kim, Soyeon; Lee, Juhyoung; Yoo, Hoi-Jun, IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.58, no.10, pp.2812 - 2825, 2023-10 |
| The Hardware and Algorithm Co-Design for Energy-Efficient DNN Processor on Edge/Mobile Devices Lee, Jinsu; Kang, Sanghoon; Lee, Jinmook; Shin, Dongjoo; Han, Donghyeon; Yoo, Hoi-Jun, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, v.67, no.10, pp.3458 - 3470, 2020-10 |
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