Showing results 4 to 6 of 6
Modeling and Analysis of a Power Distribution Network in TSV-Based 3-D Memory IC Including P/G TSVs, On-Chip Decoupling Capacitors, and Silicon Substrate Effects Kim, Ki-Yeong; Hwang, Chul-Soon; Koo, Kyoung-Choul; Cho, Jong-Hyun; Kim, Hee-Gon; Kim, Joung-Ho; Lee, Jun-Ho; et al, IEEE TRANSACTIONS ON COMPONENTS PACKAGING AND MANUFACTURING TECHNOLOGY, v.2, no.12, pp.2057 - 2070, 2012-12 |
Modeling and measurement of interlevel electromagnetic coupling and fringing effect in a hierarchical power distribution network using segmentation method with resonant cavity model Kim, Jae-Min; Jeong, You-Chul; Lee, Jun-Ho; Ryu, Chung-Hyun; Shim, Jong-Joo; Shin, Min-Chul; Kim, Joung-Ho, IEEE TRANSACTIONS ON ADVANCED PACKAGING, v.31, pp.544 - 557, 2008-08 |
PDN Impedance Modeling and Analysis of 3D TSV IC by Using Proposed P/G TSV Array Model Based on Separated P/G TSV and Chip-PDN Models Pak, Jun-So; Kim, Joo-Hee; Cho, Jong-Hyun; Kim, Ki-Yeong; Song, Tai-Gon; Ahn, Seung-Young; Lee, Jun-Ho; et al, IEEE TRANSACTIONS ON COMPONENTS PACKAGING AND MANUFACTURING TECHNOLOGY, v.1, no.2, pp.208 - 219, 2011-02 |
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