Showing results 3 to 8 of 8
A 0.13-mu m CMOS 6 Gb/s/pin Memory Transceiver Using Pseudo-Differential Signaling for Removing Common-Mode Noise Due to SSN Ha, KS; Kim, Lee-Sup; Bae, SJ; Park, KI; Choi, JS; Jun, YH; Kim, K; et al, IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.44, pp.3146 - 3162, 2009-11 |
A 4 x 10-Gb/s Referenceless-and-Masterless Phase Rotator-Based Parallel Transceiver in 90-nm CMOS Lee, Joon Yeong; Yang, Jaehyeok; Yoon, Jong Hyeok; Kwon, Soon Won; Won, Hyosup; Han, Jinho; Bae, Hyeon-Min, IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, v.24, no.6, pp.2310 - 2320, 2016-06 |
A 5.4/2.7/1.62-Gb/s Receiver for DisplayPort Version 1.2 With Multi-Rate Operation Scheme Lee, Won-Young; Hwang, Kyu-Dong; Kim, Lee-Sup, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, v.59, no.12, pp.2858 - 2866, 2012-12 |
A Fully Digital Semirotational Frequency Detection Algorithm for Bang-Bang CDRs Kwon, Soon-Won; Bae, Hyeon-Min, IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, v.27, no.12, pp.2944 - 2948, 2019-12 |
A Power-and-Area Efficient 10 x 10 Gb/s Bootstrap Transceiver in 40 nm CMOS for Referenceless and Lane-Independent Operation Lee, Joon Yeong; Han, Kwangseok; Yoon, Taehun; Kim, Taeho; Lee, Sang-Eun; Lee, Jeong-Sup; Park, Jinho; et al, IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.51, no.10, pp.2475 - 2484, 2016-10 |
An Input Data and Power Noise Inducing Clock Jitter Tolerant Reference-Less Digital CDR for LCD Intra-Panel Interface Kim, Yonghun; Lee, Taeho; Jeon, Hyun-Kyu; Lee, Dongil; Kim, Lee-Sup, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, v.64, no.4, pp.823 - 835, 2017-04 |
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