Showing results 1 to 4 of 4
A 7.1-GB/s low-power rendering engine in 2-D array-embedded memory logic CMOS for portable multimedia system Park, YH; Han, SH; Lee, JH; Yoo, Hoi-Jun, IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.36, no.6, pp.944 - 955, 2001-06 |
Bit-wise read-compare-write scheme for low power read-modify-write DRAM operation Park, YH; Choi, S; Yoo, Hoi-Jun, ELECTRONICS LETTERS, v.38, no.2, pp.62 - 63, 2002-01 |
Embedded DRAM (eDRAM) power-energy estimation using signal swing-based analytical model Park, YH; Kook, J; Yoo, Hoi-Jun, IEICE TRANSACTIONS ON ELECTRONICS, v.E85C, no.8, pp.1664 - 1668, 2002-08 |
Low-power 3D graphics processors for mobile terminals Sohn, JH; Park, YH; Yoon, CW; Woo, R; Park, SJ; Yoo, Hoi-Jun, IEEE COMMUNICATIONS MAGAZINE, v.43, pp.90 - 99, 2005-12 |
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