Browse "School of Electrical Engineering(전기및전자공학부)" by Title
Showing results 29181 to 29200 of 51041
| Parametric Evaluation of Performance Behavior in Hierarchical Storage Architecture Won, Youjip; Srivastava, Jaideep, Journal of the Hanyang Research Institute of Industrial Sciences, v.3, 2000-02 |
| Parametric expression of subthreshold slope using threshold voltage parameters for MOSFET statistical modeling Kang, SW; Min, KS; Lee, Kwyro, IEEE TRANSACTIONS ON ELECTRON DEVICES, v.43, no.9, pp.1382 - 1386, 1996-09 |
| Parametric expression of subthreshold slope using threshold voltage parameters for MOSFET statistical modeling Min, Kyeong-Sik; Lee, Kwyro, Proceedings of the 1996 IEEE International Conference on Semiconductor Electronics, ICSE, pp.50 - 53, IEEE, 1996-11-26 |
| Parametric investigation of zone melting recrystallization of polysilicon and threshold voltage model for thin SOI MOSFET = ZMR 공정의 매개변수 최적화와 얇은 SOI MOSFET에서의 문턱전압 모델link Choi, Jin-Ho; 최진호; et al, 한국과학기술원, 1992 |
| Parametric Surround modulation improves the robustness of the deep neural networks Lee, WooJu; Myung, Hyun, 10th International Conference on Robot Intelligence Technology and Applications (RiTA), pp.282 - 291, SPRINGER INTERNATIONAL PUBLISHING AG, 2022-12-07 |
| Parasitic analysis and pi-type Butterworth-Van Dyke model for complementary-metal-oxide-semiconductor Lamb wave resonator with accurate two-port Y-parameter characterizations Wang, Yong; Goh, Wang Ling; Chai, Kevin T. -C.; Mu, Xiaojing; Hong, Yan; Kropelnicki, Piotr; Je, Minkyu, REVIEW OF SCIENTIFIC INSTRUMENTS, v.87, no.4, 2016-04 |
| Parasitic BJT Read Method for High-Performance Capacitorless 1T-DRAM Mode in Unified RAM Han, Jin-Woo; Moon, Dong-Il; Kim, Dong-H; Choi, Yang-Kyu, IEEE ELECTRON DEVICE LETTERS, v.30, no.10, pp.1108 - 1110, 2009-10 |
| Parasitic capacitance optimization of GaAs HBT class E power amplifier for high efficiency CDMA EER transmitter Kim, K.Y.; Kim, J.H.; Park, S.M.; Park, Chul Soon, 2007 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2007, pp.733 - 736, 2007-06-03 |
| Parasitic Effect Analysis and Modeling for a Differential LNA Design Kim, Moon Sun; Yi, Jin Sung; Yoo, Hyung Joun, EDSSC 2003 (IEEE Conference on Electron Devices and Solid-State Circuits), pp.117 - 120, IEEE, 2003-12-17 |
| Parasitic Effect Analysis for a Differential LNA Design Kim, Moon Sun; Yi, Jin Sung; Yoo, Hyung Joun, ICM 2003 (15th International Conference on Microelectronics), pp.164 - 166, IEEE, 2003-12-10 |
| PARASITIC MESFET IN (AL, GA) AS/GAAS MODULATION DOPED FETS AND MODFET CHARACTERIZATION Lee, Kwyro; SHUR, MS; DRUMMOND, TJ; MORKOC, H, IEEE TRANSACTIONS ON ELECTRON DEVICES, v.31, no.1, pp.29 - 35, 1984 |
| Parasitic S/D resistance effects on hot-carrier reliability in body-tied FinFETs Han, JW; Lee, CH; Park, D; Choi, Yang-Kyu, IEEE ELECTRON DEVICE LETTERS, v.27, no.6, pp.514 - 516, 2006-06 |
| Pareto set selection for multiobjective stochastic simulation model Choi, Seon Han; Kim, Tag-Gon, IEEE TRANSACTIONS ON SYSTEMS MAN CYBERNETICS-SYSTEMS, v.50, no.11, pp.4256 - 4269, 2020-11 |
| PARIS and ELSA: An Elastic Scheduling Algorithm for Reconfigurable Multi-GPU Inference Servers Kim, Yunseong; Choi, Yujeong; Rhu, Minsoo, 59th ACM/IEEE Design Automation Conference, DAC 2022, pp.607 - 612, ACM/IEEE/ESDA, 2022-06-10 |
| Parity-based reliable multicast method for wireless LAN environments Yuk, Seong - Won; Cho, Dong-Ho, Vehicular Technology Conference, 1999. VTC 1999 - Fall. IEEE VTS 50th, pp.1217 - 1221, IEEE, 1999-09-19 |
| Parity-check-bit-inserted turbo code Jung H.; Lee G.; Park, Sin Chong, IEEE VTS 53rd Vehicular Technology Conference (VTS SPRING 2001), v.2, no.53ND, pp.1488 - 1491, 2001-05-06 |
| Parrern Classification of EMG Signals for Walking Motions using Self-Organizing Feature Map Lim, Jong-Tae; Choi, HL; Byun, HJ; Song, WG; Son, JW, Proc. of the 2nd International workshop on HWRS, pp.167 - 171, HWRS, 2001-01 |
| Part detection using object bounding box map attention = 객체 바운딩 박스 맵 주의 집중 역학을 사용한 부품 검출link Kwon, Jungsu; Ro, Yongman; et al, 한국과학기술원, 2019 |
| Part-based Player Identification using Deep Convolutional Representation and Multi-scale Pooling Senocak, Arda; Oh, Tae-Hyun; Kim, Junsik; Kweon, In So, IEEE/CVF Conference on Computer Vision and Pattern Recognition (CVPR), pp.1813 - 1820, IEEE, 2018-06 |
| Partial bus-invert coding for power optimization of application-specific systems Shin, Youngsoo; Chae, SI; Choi, K, IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, v.9, no.2, pp.377 - 383, 2001-04 |
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