Showing results 1 to 9 of 9
Bounded potential slack: Enabling time budgeting for dual-Vt allocation of hierarchical design Seomun, J.; Paik, S.; Shin, Youngsoo, 15th Asia and South Pacific Design Automation Conference, ASP-DAC 2010, pp.581 - 586, ASP-DAC 2010, 2010-01-18 |
Multiobjective optimization of sleep vector for zigzag power-gated circuits in standard cell elements Paik, S.; Shin, Youngsoo, 45th Design Automation Conference, DAC, pp.600 - 605, 2008-06-08 |
Pulsed-latch circuits to push the envelope of ASIC design Paik, S.; Shin, Youngsoo, 2010 International SoC Design Conference, ISOCC 2010, pp.150 - 153, ISOCC 2010, 2010-11-22 |
Pulser gating: A clock gating of pulsed-latch circuits Kim, S.; Han, I.; Paik, S.; Shin, Youngsoo, 2011 16th Asia and South Pacific Design Automation Conference, ASP-DAC 2011, pp.190 - 195, ASP-DAC 2011, 2011-01-25 |
Retiming and time borrowing: Optimizing high-performance pulsed-latch-based circuits Lee, S.; Paik, S.; Shin, Youngsoo, 2009 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2009, pp.375 - 380, ACM SIGDA and IEEE CEDA, 2009-11-02 |
Selectively patterned masks: Beyond structured ASIC Baek, D.; Shin, I.; Paik, S.; Shin, Youngsoo, 2010 International SoC Design Conference, ISOCC 2010, pp.154 - 157, ISOCC 2010, 2010-11-22 |
Statistical mixed Vt allocation of body-biased circuits for reduced leakage variation Jeong, J.; Paik, S.; Shin, Youngsoo, 2008 Asia and South Pacific Design Automation Conference, ASP-DAC, pp.629 - 634, ACM Special Interest Group on Design Automation (SIGDA), 2008-03-21 |
Statistical time borrowing for pulsed-latch circuit designs Paik, S.; Yu, L.-E.; Shin, Youngsoo, 2010 15th Asia and South Pacific Design Automation Conference, ASP-DAC 2010, pp.675 - 680, ASP-DAC 2010, 2010-01-18 |
Wakeup synthesis and its buffered tree construction for power gating circuit designs Paik, S.; Kim, S.; Shin, Youngsoo, 16th ACM/IEEE International Symposium on Low-Power Electronics and Design, ISLPED'10, pp.413 - 418, ACM/IEEE, 2010-08-18 |
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