Showing results 2 to 7 of 7
Pin Accessibility-Driven Cell Layout Redesign and Placement Optimization Seo, Jaewoo; Jung, Jinwook; Kim, Sangmin; Shin, Youngsoo, 54th Annual Design Automation Conference, DAC 2017, pp.1 - 6, Institute of Electrical and Electronics Engineers Inc., 2017-06-20 |
Pulsed-latch ASIC Synthesis in Industrial Design Flow Kim, Sangmin; Kim, Duckhwan; Shin, Youngsoo, Asia and South Pacific Design Automation Conference, pp.356 - 361, IEEE, 2013-01 |
Pulsed-Latch Aware Placement for Timing-Integrity Optimization Chuang, Yi-Lin; Kim, Sangmin; Shin, Youngsoo; Chang, Yao-Wen, IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, v.30, no.12, pp.1856 - 1869, 2011-12 |
Synthesis and optimization of dual operational-mode circuits = 듀얼 동작 모드 회로의 합성과 최적화link Kim, Sangmin; 김상민; et al, 한국과학기술원, 2016 |
Synthesis of Dual-Mode Circuits Through Library Design, Gate Sizing, and Clock-Tree Optimization Kim, Sangmin; Kang, Seokhyeong; Shin, Youngsoo, ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS, v.21, no.3, 2016-07 |
Wakeup scheduling and its buffered tree synthesis for power gating circuits Kim, Sangmin; Paik, Seungwhun; Kang, Seokhyeong; Shin, Youngsoo, INTEGRATION-THE VLSI JOURNAL, v.53, pp.157 - 170, 2016-03 |
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