Development of 500-MHz low-complexity ADFLL as reference clock generator for FPGA

Abstract

We report the development of an on-chip 500 MHz reference clock generator that will be integrated into a clock manager of a field-programmable gate array (FPGA). The generator is implemented in the form of an all-digital frequency locked loop (ADFLL) with the architecture of low complexity and high modularity. To accomplish this architecture, we propose a new circuit that converts a frequency difference into a proportional distributed pulse width. The combination of the proposed circuit and a conventional phase-and-frequency detector is found to form a complete frequency comparator that can simply indicate all possibly occurring conditions particularly when two frequencies are compared with each other, i.e., (1) equal to, (2) lower than, or (3) higher than. In further development, we also design and implement circuits that can distinctly mark the border between the steady state and the transient state of the ADFLL. These circuits enable a particular exploitation on the transient state of the ADFLL so that the locking time can be significantly improved. The developed ADFLL was success-fully implemented in a 0.13 um CMOS technology, was found to consume 3 mW with 1.2 V supply while oper-ating at 500 MHz and being driven by a 10 MHz reference clock, and also had the order of 60 us of locking time.