Design of pipelined cache DRAM for fast random-access

Abstract

In this thesis, a new DRAM core called Pipelined Cache DRAM (PCDRAM) is proposed. A multi-bank architecture and bank interleaving techniques made possible fast row operation (typically at 1/tRC). Contrary to other multi-bank approaches, PCDRAM has no penalty for random-access even in the case that all requests are issued to the identical bank. In other words, PCDRAM perfectly ensures the penalty-free operation. The penalty-free means that PCDRAM operates at fast row cycle, regardless of whether cache hit/miss occurs or not and of whether the successive requests are for the same bank or for the different banks. Because of invariant and fast row cycle operation, PCDRAM can offer SRAM-like interface to an external system like microprocessors, except for the need of periodic refresh operation. This is realized by two additional DRAM caches, innovative Micro Core Operation, and some circuit techniques. For low power DRAM core operation, a novel bit line control scheme, Single Bit line Writing (SBW) scheme, is also proposed. Using SBW, The power consumption can be reduced in the core by 22% compared with the conventional DRAM core.