Clock mesh design for multi-level clock gating

Abstract

Power and clock skew are most commonly mentioned challenges in VLSI design. Clock gating is one of the most popular technique for power reduction. Clock gating shuts down a clock network that drives sequential elements in unswitching state to reduce clock power consumption. Clock mesh is one of the clock distribution network utilizes mesh shaped wire grids for clock distribution. Clock signals arrive at mesh grid differently, but mesh grids averages these signals and therefore, resulting clock skew is quite smaller than normal clock tree. In this thesis, clock mesh is applied to hierarchically clock gated circuit. Three methods are proposed: single mesh, mulitple mesh (overlapped and non-overlapped.) The purpose of this thesis is suggest a guideline for designers who wants to implement a clock mesh to their design, which employs clock gating. Power consumption, clock skew, wirelengths of clock network, timing closure of these design methods will be discussed experimentally. Single consumes 16.2% more power than overlapped mesh because overlapped mesh has more gating chances to gate clock network including mesh grid and premesh tree. However, overlapped mesh’s clock wirelengths, clock skew, and, design time are larger than single mesh’s because of mulitple mesh implementation. In addition, floorplanning can be employed before placement, to get a non-overlapped mesh implementation. Floorplanning limits module’s area to assigned areas, therefore, meshes are not overlapped in non-overlapped mesh implementation. As a result, overlapped mesh consumes 4.7% more power than non-overlapped mesh method. However, designer must decide whether or not to use this method at early design stage because, critical path delay increases. Mesh power estimation method is also proposed: single and overlapeed mesh’s mesh grid switching capacitance are compared before actual mesh construction.