Eye diagram estimation including crosstalk effect for high-speed channel on PCB, silicon and glass interposer

Abstract

Recently, data rate of high-speed channel especially for GDDR is getting increase over 10 Gbps/pin. To have wide bandwidth, number of I/O increases and metal space is going to be very narrow. Hence, cross-talk issue has become more important. On high-speed channel, input signals are degraded by many reasons such as crosstalk effect, channel loss, and ISI. These factors limit the data rate of the channel. Even differen-tial signaling, which has strong external noise immunity, is affected by crosstalk effect because of narrow metal space. Therefore, signal integrity analysis for high-speed channel is required. Eye diagram is easy to check the signal integrity of high-speed channel that is a convenient graphical metrics to analyze received signals at receiver. As data rate increases, deterministic jitter became the dominant jitter component which is considered in worst eye diagram. Previous researches for worst eye diagram estimation have limitations for high-speed channel. In this thesis, precise and fast eye diagram estimation method is proposed. Proposed eye diagram esti-mation method is able to consider crosstalk effect and be used for two and three channels system. This pro-posed method can be applied for single-ended and differential signaling channels on various substrates such as PCB, silicon and glass interposer. Eye diagrams of silicon and glass interposer channels with same dimension are compared. In addition, using this proposed method, eye diagrams of crosstalk reduction schemes, wide space and wide space with guard trace, are estimated and analyzed.