Fast and accurate hierarchical hybrid modeling and measurement verification of external electromagnetic noise effects on ADC in chip-pcb structure

Abstract

In this thesis, a model of external electromagnetic noise effects on an analog-to-digital converter (ADC) in a hierarchical structure is proposed. We target two types of external electromagnetic noise effects, one is the simultaneous switching noise effects, and the other is the magnetic field effects. These targeted noise effects are determined to consider possible promising technology such as high speed digital circuit, and wireless power transfer technology. The ADC performance is determined by not only on-chip characteristics but also off-chip characteristics. Therefore, chip-package-printed circuit board (PCB) co-analysis and co-modeling are required to accurately evaluate the performance of the ADC. We propose the co-model which allows the estimation and analysis of external electromagnetic noise effects on the ADC including the characteristics of off-chip/magnetic-field. To validate the proposed models, an ADC was fabricated by a 0.13 μm CMOS process and wire bonded to the designed PCB. The effective number of bits (ENOB) of the ADC was measured by sweeping the electromagnetic noise frequency to discover which noise frequency is critical to an ADC designed with a chip-PCB hierarchical structure. The results estimated by the proposed model correlated well with the co-simulated and measured results. The proposed modeling procedure saves the chip and PCB designers time and computation resources to achieve high-quality analog devices or mixed-mode systems and provides an intuitive understanding of the noise effect.