Low voltage design of pipeline architecture through one-cycle correction of timing errors단일 사이클 페널티를 갖는 타이밍 오류 정정 기법을 이용한 저전압 파이프라인 아키텍처 설계

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The introduction of a timing guardband is the standard way of addressing variability in circuit delay. A designer adds just enough timing guardband to the critical path delay to make a circuit operate correctly in the worst case. However, as technology scales down to the deep submicron nodes, process variations as well as dynamic fluctuations of supply voltage, temperature, and noise have much larger impact on the delay. As a result of these changes, timing guardband has grown very large in deep submicron technology, motivating the development of design methodologies which reduce this guardband. The main challenge in producing a viable scheme for timing guardband reduction is the increased probability of the circuit operating incorrectly. A number of methods have been proposed to address this problem, and they can be classified as error prediction and error correction. Error prediction uses sensors or canary-circuits to monitor the magnitude of timing variations to predict timing errors, and adjusts the supply voltage or clock frequency, or both, before errors actually occur. These methods are effective in measuring global and static variations in the factors which affect timing, but they cannot detect temporal variations due to dynamic noise or local variation, which continue to require a timing guardband. The error detection approach uses error detection sequential (EDS) elements to detect the errors that actually occur, and correct them using on-chip correction logic. Razor is a well-known EDS element, in which data is captured by a shadow latch with a delayed clock signal, as well as by a main flip-flop with a nominal clock. If the shadow latch data is different from that captured by the main flip-flop, an error is flagged. Since the error correction approach detects changes which occur on the actual critical path, the timing guardband which would otherwise be required to allow for temporal and local variations can be eliminated, as well as the guardband f...
Advisors
Shin, Young-Sooresearcher신영수
Description
한국과학기술원 : 전기및전자공학과,
Publisher
한국과학기술원
Issue Date
2014
Identifier
591817/325007  / 020095319
Language
eng
Description

학위논문(박사) - 한국과학기술원 : 전기및전자공학과, 2014.8, [ viii, 95p ]

Keywords

timing speculation; low voltage operation; Pipeline; 오류 정정; error correction; 저전압 설계; 파이프라인 회로

URI
http://hdl.handle.net/10203/196589
Link
http://library.kaist.ac.kr/search/detail/view.do?bibCtrlNo=591817&flag=dissertation
Appears in Collection
EE-Theses_Ph.D.(박사논문)
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