Channel dispersion-tolerant referenceless frequency acquisition technique by using a stochastic reference clock generator

Abstract

As the required data rate increases, a multi-channel clock and data recovery (CDR) are being employed in serial links to overcome the throughput limitation of a CDR, which is set by the channel bandwidth. Furthermore, independent channel and referenceless system are demanded in high-speed wire-line industries. This work presents : (1) a theoretical analysis of the stochastic reference clock generator (SRCG), which creates a clock-like periodic signal from a random non-return-to-zero (NRZ) data sequence for the masterless and referenceless clock generator. The output of the SRCG can be utilized as a reference clock for frequency acquisition in dual-loop clock-and-data recovery (CDR) circuits. A frequency locked loop (FLL) subsequent to the SRCG guides the voltage controlled oscillator (VCO) frequency into the pull-in range of the phase locked loop while suppressing the high-frequency phase noise of the SRCG. The phase noise and frequency offset of the SRCG-FLL pair are analyzed. The validity of the theoretical analysis is supported by results taken from a test chip. (2) A phase-rotator-based 4-channel digital clock and data recovery (CDR) IC featuring a low-power dispersion-tolerant reference-less frequency acquisition technique is presented. A quasi-periodic reference clock signal extracted directly from a dispersed input signal is distributed to digitally controlled phase rotators in the CDR ICs for phase acquisition. A multiphase frequency-acquisition scheme is employed for the reduction of the clock jitter. The measurement results show that the proposed design offers a lower frequency offset and clock noise floor under channel dispersion, as compared to conventional designs. (3) A masterless and referenceless clock generator for $4\times\unit[25\mbox{-}]{Gb/s}$ parallel transceiver is presented finally. Entire channels operate independently without performance penalty while saving power and area. A jitter suppression-loop (JSL) is incorporated per channel t...