DC Field | Value | Language |
---|---|---|
dc.contributor.advisor | Kim, Lee-Sup | - |
dc.contributor.advisor | 김이섭 | - |
dc.contributor.author | Kim, Hong-Yun | - |
dc.contributor.author | 김홍윤 | - |
dc.date.accessioned | 2015-04-23T06:12:22Z | - |
dc.date.available | 2015-04-23T06:12:22Z | - |
dc.date.issued | 2012 | - |
dc.identifier.uri | http://library.kaist.ac.kr/search/detail/view.do?bibCtrlNo=568066&flag=dissertation | - |
dc.identifier.uri | http://hdl.handle.net/10203/196517 | - |
dc.description | 학위논문(박사) - 한국과학기술원 : 전기및전자공학과, 2012.2, [ ix, 109 p. ] | - |
dc.description.abstract | Ray tracing is a technique for rendering a 2D image from 3D objects by tracing the paths of light through pixels in the 2D image screen and simulating the effects of encounters with the 3D objects. Ray trac-ing takes various paths of light, the sources of global illumination, into accounts when it calculates the color of a pixel so that it is usually capable of producing a very high degree of visual realism than that of typical rasterization methods. To achieve the high realism, it needs massive computing power, especially floating-point (FP) calculations. A single-instruction, multiple-thread (SIMT) based ray tracing processor provides massive computing power, but it suffers from two problems, branch divergence and shared memory conten-tion. In this dissertation we present a mobile ray tracing processor (MRTP) that is based on multiple cores of reconfigurable SIMT processor to mitigate the performance degradation due to both branch divergence and shared memory contention. We present the analysis results of ray tracing, and propose two types of reconfigurable SIMT architectures (R-SIMT I and R-SIMT II) to improve the SIMT processor’s utilization that is prone to significantly decrease due to branch divergence. R-SIMT I is configured as scalar SIMT to execute a regular kernel without branch instructions, and is reconfigured as vector SIMT to execute an irregu-lar kernel with branch instructions. R-SIMT II is configured as one wide SIMT to execute a regular kernel, and is reconfigured as multiple-instruction, multiple data (MIMD) architecture. Shared memory contention is alleviated by both an access managing unit and a new time-division multiplexing with multi-phase clocks to hide arbitration delays. The performance improvements of proposed reconfigurable SIMT architectures are evaluated using simulation results collected from both a ray tracing program and a cycle-accurate GPU simulator. The utilization of R-SIMT I is improved by 19.9% compared to a conventiona... | eng |
dc.language | eng | - |
dc.publisher | 한국과학기술원 | - |
dc.subject | mobile processor | - |
dc.subject | multi-core | - |
dc.subject | reconfigurable SIMT | - |
dc.subject | 레이 트레이싱 | - |
dc.subject | Ray tracing | - |
dc.subject | 멀티 코어 프로세서 | - |
dc.subject | SIMT 구조 | - |
dc.title | (A) Mobile Ray Tracing Processor with Reconfigurable SIMT Multi-Core for High Datapath Utilization | - |
dc.title.alternative | 구조변경 가능한 SIMT 멀티코어 기반의 모바일 레이 트레이싱 프로세서 | - |
dc.type | Thesis(Ph.D) | - |
dc.identifier.CNRN | 568066/325007 | - |
dc.description.department | 한국과학기술원 : 전기및전자공학과, | - |
dc.identifier.uid | 020085057 | - |
dc.contributor.localauthor | Kim, Lee-Sup | - |
dc.contributor.localauthor | 김이섭 | - |
Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.