DC Field | Value | Language |
---|---|---|
dc.contributor.author | Kim, Yonghun | ko |
dc.contributor.author | Kim, Young Ju | ko |
dc.contributor.author | Lee, Taeho | ko |
dc.contributor.author | Kim, Lee-Sup | ko |
dc.date.accessioned | 2015-04-08T08:05:17Z | - |
dc.date.available | 2015-04-08T08:05:17Z | - |
dc.date.created | 2014-07-08 | - |
dc.date.created | 2014-07-08 | - |
dc.date.created | 2014-07-08 | - |
dc.date.issued | 2015-03 | - |
dc.identifier.citation | IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, v.23, no.3, pp.588 - 592 | - |
dc.identifier.issn | 1063-8210 | - |
dc.identifier.uri | http://hdl.handle.net/10203/195962 | - |
dc.description.abstract | As the data rate has been increased over 10 Gb/s with copper interconnect, the intersymbol interference (ISI) caused from the channel loss should be compensated. While a decision feedback equalizer (DFE), which is widely used in the receiver can compensate the ISI, its ability to enhance the signal-to-noise ratio (SNR) is limited especially for high frequency data patterns (alternating data patterns). Even a DFE with a large number of taps, which has powerful compensation capacity for ISI, can improve only limited amount of SNR. To improve SNR, this brief presents a 1/4th baud-rate continuous-time linear equalizer (CTLE) and a two-tap DFE. The 1/4th baud-rate CTLE recovers data to be adequate for the DFE, and remaining ISI is removed by the DFE. To boost the high frequency gain of the DFE, exclusive OR merged adders are introduced, so the proposed equalizer is more tolerant against channel noise. It compensates 21.7-dB channel loss and operates with 11.5-Gb/s data rate as it consumes 25.35 mW from 1.3 V supply in a 110-nm CMOS technology. | - |
dc.language | English | - |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.subject | DECISION-FEEDBACK EQUALIZER | - |
dc.subject | 45-NM SOI CMOS | - |
dc.subject | TECHNOLOGY | - |
dc.subject | TRANSCEIVER | - |
dc.title | An 11.5 Gb/s 1/4th Baud-Rate CTLE and Two-Tap DFE With Boosted High Frequency Gain in 110-nm CMOS | - |
dc.type | Article | - |
dc.identifier.wosid | 000350208700018 | - |
dc.identifier.scopusid | 2-s2.0-85027922395 | - |
dc.type.rims | ART | - |
dc.citation.volume | 23 | - |
dc.citation.issue | 3 | - |
dc.citation.beginningpage | 588 | - |
dc.citation.endingpage | 592 | - |
dc.citation.publicationname | IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS | - |
dc.identifier.doi | 10.1109/TVLSI.2014.2314147 | - |
dc.contributor.localauthor | Kim, Lee-Sup | - |
dc.type.journalArticle | Article | - |
dc.subject.keywordAuthor | Continuous-time linear equalizers (CTLEs) | - |
dc.subject.keywordAuthor | decision feedback equalizers (DFEs) | - |
dc.subject.keywordAuthor | equalizer | - |
dc.subject.keywordAuthor | intersymbol interference (ISI) | - |
dc.subject.keywordPlus | DECISION-FEEDBACK EQUALIZER | - |
dc.subject.keywordPlus | 45-NM SOI CMOS | - |
dc.subject.keywordPlus | TECHNOLOGY | - |
dc.subject.keywordPlus | TRANSCEIVER | - |
Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.