Low-Complexity Tree Architecture for Finding the First Two Minima
| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | Lee, Youngjoo | ko |
| dc.contributor.author | Kim, Bongjin | ko |
| dc.contributor.author | Jung, Jaehwan | ko |
| dc.contributor.author | Park, In-Cheol | ko |
| dc.date.accessioned | 2015-04-07T04:46:17Z | - |
| dc.date.available | 2015-04-07T04:46:17Z | - |
| dc.date.created | 2014-11-25 | - |
| dc.date.created | 2014-11-25 | - |
| dc.date.issued | 2015-01 | - |
| dc.identifier.citation | IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, v.62, no.1, pp.61 - 64 | - |
| dc.identifier.issn | 1549-7747 | - |
| dc.identifier.uri | http://hdl.handle.net/10203/195203 | - |
| dc.description.abstract | This brief presents an area-efficient tree architecture for finding the first two minima as well as the index of the first minimum, which is essential in the design of a low-density parity-check decoder based on the min-sum algorithm. The proposed architecture reduces the number of comparators by reusing the intermediate comparison results computed for the first minimum in order to collect the candidates of the second minimum. As a result, the proposed tree architecture improves the area-time complexity remarkably. | - |
| dc.language | English | - |
| dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
| dc.subject | VALUES | - |
| dc.title | Low-Complexity Tree Architecture for Finding the First Two Minima | - |
| dc.type | Article | - |
| dc.identifier.wosid | 000347326200013 | - |
| dc.identifier.scopusid | 2-s2.0-84920829049 | - |
| dc.type.rims | ART | - |
| dc.citation.volume | 62 | - |
| dc.citation.issue | 1 | - |
| dc.citation.beginningpage | 61 | - |
| dc.citation.endingpage | 64 | - |
| dc.citation.publicationname | IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS | - |
| dc.identifier.doi | 10.1109/TCSII.2014.2362663 | - |
| dc.contributor.localauthor | Park, In-Cheol | - |
| dc.contributor.nonIdAuthor | Lee, Youngjoo | - |
| dc.type.journalArticle | Article | - |
| dc.subject.keywordAuthor | Area-efficient design | - |
| dc.subject.keywordAuthor | digital integrated circuits | - |
| dc.subject.keywordAuthor | low-density parity-check (LDPC) codes | - |
| dc.subject.keywordAuthor | minimum value generation | - |
| dc.subject.keywordAuthor | tree structure | - |
| dc.subject.keywordPlus | VALUES | - |
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