Auto-Scaling Overdrive Method Using Adaptive Charge Amplification for PRAM Write Performance Enhancement

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dc.contributor.authorChoi, Sukhwanko
dc.contributor.authorKim, Hyun-Sikko
dc.contributor.authorJung, Seungchulko
dc.contributor.authorSung, Si-Dukko
dc.contributor.authorYuk, Young-Subko
dc.contributor.authorYim, Hyuck-Sangko
dc.contributor.authorShin, Yoonjaeko
dc.contributor.authorCheon, Jun-Hoko
dc.contributor.authorAhn, Changyongko
dc.contributor.authorKim, Taekseungko
dc.contributor.authorKim, Yongki Braveko
dc.contributor.authorCho, Gyu-Hyeongko
dc.date.accessioned2015-01-29T07:00:19Z-
dc.date.available2015-01-29T07:00:19Z-
dc.date.created2014-11-21-
dc.date.created2014-11-21-
dc.date.created2014-11-21-
dc.date.created2014-11-21-
dc.date.issued2014-11-
dc.identifier.citationIEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, v.61, no.11, pp.3165 - 3174-
dc.identifier.issn1549-8328-
dc.identifier.urihttp://hdl.handle.net/10203/193811-
dc.description.abstractA PRAM write driver with an auto-scaling overdrive method is presented. The proposed overdrive method significantly reduces the rise time of the cell-current pulse for bit-line parasitic components of 3 pF and 6 k Omega, and it lowers the complexity of the overdrive control using an adaptive charge amplification technique. A rise time of less than 15 ns is achieved and shortened up to 4.7 times, and the total write-throughput is increased. The rise time is reduced consistently for all levels of the target-current by the auto-scaling effect. Therefore, cell heating control becomes more linear in program-and-verify (PNV) operation. Due to its simple adding-on structure, it is easily compatible with a conventional write driver. A prototype chip was implemented using a 0.18-mu m CMOS process. It is also applicable to smaller-scale technology.-
dc.languageEnglish-
dc.publisherIEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC-
dc.titleAuto-Scaling Overdrive Method Using Adaptive Charge Amplification for PRAM Write Performance Enhancement-
dc.typeArticle-
dc.identifier.wosid000344467500012-
dc.identifier.scopusid2-s2.0-84908455751-
dc.type.rimsART-
dc.citation.volume61-
dc.citation.issue11-
dc.citation.beginningpage3165-
dc.citation.endingpage3174-
dc.citation.publicationnameIEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS-
dc.identifier.doi10.1109/TCSI.2014.2334813-
dc.contributor.localauthorKim, Hyun-Sik-
dc.contributor.localauthorCho, Gyu-Hyeong-
dc.contributor.nonIdAuthorYim, Hyuck-Sang-
dc.contributor.nonIdAuthorShin, Yoonjae-
dc.contributor.nonIdAuthorCheon, Jun-Ho-
dc.contributor.nonIdAuthorAhn, Changyong-
dc.contributor.nonIdAuthorKim, Taekseung-
dc.contributor.nonIdAuthorKim, Yongki Brave-
dc.description.isOpenAccessN-
dc.type.journalArticleArticle-
dc.subject.keywordAuthorMulti-level cell (MLC)-
dc.subject.keywordAuthoroverdrive-
dc.subject.keywordAuthorphase change random access memory (PRAM)-
dc.subject.keywordAuthorphase-change memory-
dc.subject.keywordAuthorprogram-and-verify (PNV)-
dc.subject.keywordAuthorwrite driver-
dc.subject.keywordAuthorMulti-level cell (MLC)-
dc.subject.keywordAuthoroverdrive-
dc.subject.keywordAuthorphase change random access memory (PRAM)-
dc.subject.keywordAuthorphase-change memory-
dc.subject.keywordAuthorprogram-and-verify (PNV)-
dc.subject.keywordAuthorwrite driver-
dc.subject.keywordAuthorMulti-level cell (MLC)-
dc.subject.keywordAuthoroverdrive-
dc.subject.keywordAuthorphase change random access memory (PRAM)-
dc.subject.keywordAuthorphase-change memory-
dc.subject.keywordAuthorprogram-and-verify (PNV)-
dc.subject.keywordAuthorwrite driver-
dc.subject.keywordPlusPHASE-CHANGE MEMORY-
dc.subject.keywordPlusTECHNOLOGY-
dc.subject.keywordPlusTHROUGHPUT-
dc.subject.keywordPlusPHASE-CHANGE MEMORY-
dc.subject.keywordPlusTECHNOLOGY-
dc.subject.keywordPlusTHROUGHPUT-
dc.subject.keywordPlusPHASE-CHANGE MEMORY-
dc.subject.keywordPlusTECHNOLOGY-
dc.subject.keywordPlusTHROUGHPUT-
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