DC Field | Value | Language |
---|---|---|
dc.contributor.author | Ziabari, Amirkoushyar | ko |
dc.contributor.author | Park, Je-Hyoung | ko |
dc.contributor.author | Ardestani, Ehsan K. | ko |
dc.contributor.author | Renau, Jose | ko |
dc.contributor.author | Kang, Sung-Mo | ko |
dc.contributor.author | Shakouri, Ali | ko |
dc.date.accessioned | 2015-01-29T06:59:49Z | - |
dc.date.available | 2015-01-29T06:59:49Z | - |
dc.date.created | 2014-12-19 | - |
dc.date.created | 2014-12-19 | - |
dc.date.issued | 2014-11 | - |
dc.identifier.citation | IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, v.22, no.11, pp.2366 - 2379 | - |
dc.identifier.issn | 1063-8210 | - |
dc.identifier.uri | http://hdl.handle.net/10203/193806 | - |
dc.description.abstract | High-temperature and temperature nonuniformity in high-performance integrated circuits (ICs) can significantly degrade chip performance and reliability. Thus, accurate temperature information is a critical factor in chip design and verification. Conventional volume grid-based techniques, such as finite-difference and finite-element methods (FEMs), are computationally expensive. In an effort to reduce the computation time, we have developed a new method, called power blurring (PB), for calculating temperature distributions using a matrix convolution technique in analogy with image blurring. The PB method considers the finite size and boundaries of the chip as well as 3-D heat spreading in the heat sink. PB is applicable to both static and transient thermal simulations. Comparative studies with a commercial FEM tool show that the PB method is accurate within 2%, with orders of magnitude speedup compared with FEM methods. PB can be applied to very fine power maps with a grid size as small as 10 mu m for a fully packaged IC or submicrometer heat sources in power electronic transistor arrays. In comparison with architecture-level thermal simulators, such as HotSpot, PB provides much more accurate temperature profiles with reduced computation time. | - |
dc.language | English | - |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.subject | CHIP | - |
dc.subject | SIMULATION | - |
dc.subject | DESIGN | - |
dc.subject | MANAGEMENT | - |
dc.subject | PROFILE | - |
dc.subject | MODEL | - |
dc.title | Power Blurring: Fast Static and Transient Thermal Analysis Method for Packaged Integrated Circuits and Power Devices | - |
dc.type | Article | - |
dc.identifier.wosid | 000344483200013 | - |
dc.identifier.scopusid | 2-s2.0-84908461480 | - |
dc.type.rims | ART | - |
dc.citation.volume | 22 | - |
dc.citation.issue | 11 | - |
dc.citation.beginningpage | 2366 | - |
dc.citation.endingpage | 2379 | - |
dc.citation.publicationname | IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS | - |
dc.identifier.doi | 10.1109/TVLSI.2013.2293422 | - |
dc.contributor.nonIdAuthor | Ziabari, Amirkoushyar | - |
dc.contributor.nonIdAuthor | Park, Je-Hyoung | - |
dc.contributor.nonIdAuthor | Ardestani, Ehsan K. | - |
dc.contributor.nonIdAuthor | Renau, Jose | - |
dc.contributor.nonIdAuthor | Shakouri, Ali | - |
dc.type.journalArticle | Article | - |
dc.subject.keywordAuthor | Finite-element method (FEM) | - |
dc.subject.keywordAuthor | heat transfer | - |
dc.subject.keywordAuthor | integrated circuits (ICs) | - |
dc.subject.keywordAuthor | package | - |
dc.subject.keywordAuthor | power electronics | - |
dc.subject.keywordAuthor | temperature | - |
dc.subject.keywordAuthor | thermal management | - |
dc.subject.keywordAuthor | thermal simulation | - |
dc.subject.keywordPlus | CHIP | - |
dc.subject.keywordPlus | SIMULATION | - |
dc.subject.keywordPlus | DESIGN | - |
dc.subject.keywordPlus | MANAGEMENT | - |
dc.subject.keywordPlus | PROFILE | - |
dc.subject.keywordPlus | MODEL | - |
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