A Time-Domain High-Order MASH Delta Sigma ADC Using Voltage-Controlled Gated-Ring Oscillator

Abstract

In this paper, a time-domain high-order Delta Sigma analog-to-digital converter (ADC) using voltage-controlled gated-ring oscillator (VC-GRO) and time-domain multi-stage-noise-shaping (MASH) is introduced. To implement the high-order noise transfer function (NTF), a voltage-controlled oscillator (VCO) and VC-GRO quantizers are cascaded. Unlike conventional high-order Delta Sigma ADC using feedback loop, the proposed ADC has advantages that the architecture is open-loop and the quantizer resolution depends on the time resolution, thus making it attractive for deep submicron CMOS process. The performance of the proposed ADC is theoretically analyzed and simulated, including non-ideal conditions such as nonlinearity, mismatch, propagation delay of logic gates, phase noise, and sampling clock jitter.