DC Field | Value | Language |
---|---|---|
dc.contributor.author | Han, Jinho | ko |
dc.contributor.author | Won, Hyo Sup | ko |
dc.contributor.author | Bae, Hyeon-Min | ko |
dc.date.accessioned | 2014-09-01T08:08:53Z | - |
dc.date.available | 2014-09-01T08:08:53Z | - |
dc.date.created | 2014-07-10 | - |
dc.date.created | 2014-07-10 | - |
dc.date.issued | 2014-06 | - |
dc.identifier.citation | IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, v.22, no.6, pp.1219 - 1225 | - |
dc.identifier.issn | 1063-8210 | - |
dc.identifier.uri | http://hdl.handle.net/10203/189413 | - |
dc.description.abstract | A 0.6-2.7-Gb/s phase-rotator-based four-channel digital clock and data recovery (CDR) IC featuring a low-power dispersion-tolerant referenceless frequency acquisition technique is presented. A quasi-periodic reference clock signal extracted directly from a dispersed input signal is distributed to digitally controlled phase rotators in the CDR ICs for phase acquisition. A multiphase frequency acquisition scheme is employed for the reduction of the clock jitter. The measurement results show that the proposed design offers a lower frequency offset and clock noise floor under channel dispersion, as compared with conventional designs. The proposed four-channel digital CDR IC is fabricated in a 90-nm CMOS process. The figure of merit for a single channel is 8 mW/Gb/s such as a feedforward equalizer, a decision-feedback equalizer, and a referenceless CDR. | - |
dc.language | English | - |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.subject | DATA RECOVERY CIRCUIT | - |
dc.subject | SERIAL-LINK | - |
dc.subject | CLOCK | - |
dc.subject | EQUALIZATION | - |
dc.title | 0.6-2.7-Gb/s Referenceless Parallel CDR With a Stochastic Dispersion-Tolerant Frequency Acquisition Technique | - |
dc.type | Article | - |
dc.identifier.wosid | 000337167600002 | - |
dc.identifier.scopusid | 2-s2.0-84901627846 | - |
dc.type.rims | ART | - |
dc.citation.volume | 22 | - |
dc.citation.issue | 6 | - |
dc.citation.beginningpage | 1219 | - |
dc.citation.endingpage | 1225 | - |
dc.citation.publicationname | IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS | - |
dc.identifier.doi | 10.1109/TVLSI.2013.2268862 | - |
dc.embargo.liftdate | 9999-12-31 | - |
dc.embargo.terms | 9999-12-31 | - |
dc.contributor.localauthor | Bae, Hyeon-Min | - |
dc.type.journalArticle | Article | - |
dc.subject.keywordAuthor | Clock and data recovery (CDR) | - |
dc.subject.keywordAuthor | data-divider | - |
dc.subject.keywordAuthor | dispersion | - |
dc.subject.keywordAuthor | frequency-locked loop (FLL) | - |
dc.subject.keywordAuthor | parallel CDR | - |
dc.subject.keywordAuthor | phase rotator | - |
dc.subject.keywordAuthor | referenceless | - |
dc.subject.keywordPlus | DATA RECOVERY CIRCUIT | - |
dc.subject.keywordPlus | REFERENCE CLOCK | - |
dc.subject.keywordPlus | SERIAL-LINK | - |
dc.subject.keywordPlus | EQUALIZATION | - |
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