A Type-I Delta Sigma Fractional-N Frequency Synthesizer Adopting a New Discrete-Time Loop Filter

Abstract

In this letter, a type-I Delta Sigma fractional-N frequency synthesizer adopting a new discrete-time loop filter (DTLF) is proposed. By means of assigning an additional pair of switched capacitors to the conventional first order DTLF architecture, cascaded capacitor-sharing operation is implemented, providing a second order infinite impulse response (IIR) filtering characteristic. The sufficiently high slope of the proposed second order DTLF lessens the need for additional passive filters in quantization noise suppression, thereby reducing the active chip area. Implemented in a 65 nm CMOS process, the proposed synthesizer occupies only 0.25 mm(2), operates over a frequency range of 400 to 900 MHz with less than 10 Hz resolution, and consumes 4.7 mA from a 1 V supply. The measurement shows phase noise of -100.05 dBc/Hz and -128.29 dBc/Hz at 100 kHz and 1 MHz offsets, respectively, for 773 MHz operating frequency.