A 57 mW 12.5 mu J/Epoch Embedded Mixed-Mode Neuro-Fuzzy Processor for Mobile Real-Time Object Recognition

Abstract

A digital/analog mixed-mode processor is proposed to realize low-power and real-time neuro-fuzzy system for mobile object recognition. It integrates 1024 highly-parallel analog processing element for high dimensional inference operation, and accurate and fast digital accelerator for cascaded learning operation of neuro-fuzzy network. A neuro-fuzzy controller is proposed to manage the mixed-mode operations as a host processor while reducing extra processing delay and power consumption on inter-domain communications. To solve the conventional problems of a large dimensional mixed-mode VLSI system such as throughput degradation due to long channel delay, limited functionality of fixed analog circuits, and mismatches from process variation, the proposed processor adopts 2-stage asynchronous mixed-mode pipeline, flexible channel configuration of each domain, and learning-based calibration technologies respectively. As a result, the processor only consumes 57 mW on average and obtains 12.5 mu J/epoch energy efficiency for on-line learning mixed-mode neuro-fuzzy system with 50 fuzzy rules.