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College of Engineering(공과대학)School of Electrical Engineering(전기및전자공학부)EE-Conference Papers(학술회의논문)

High frequency electrical model of through wafer via for 3-D stacked chip packaging

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dc.contributor.authorRyu, C.ko
dc.contributor.authorLee, J.ko
dc.contributor.authorLee, H.ko
dc.contributor.authorLee, K.ko
dc.contributor.authorOh, T.ko
dc.contributor.authorKim, Jounghoko
dc.date.accessioned2010-06-01T06:35:00Z-
dc.date.available2010-06-01T06:35:00Z-
dc.date.created2012-02-06-
dc.date.created2012-02-06-
dc.date.issued2006-09-05-
dc.identifier.citationESTC 2006 - 1st Electronics Systemintegration Technology Conference, pp.215 - 220-
dc.identifier.urihttp://hdl.handle.net/10203/18703-
dc.languageEnglish-
dc.language.isoen_USen
dc.publisherIEEE-
dc.titleHigh frequency electrical model of through wafer via for 3-D stacked chip packaging-
dc.typeConference-
dc.identifier.wosid000241425800032-
dc.identifier.scopusid2-s2.0-42549142869-
dc.type.rimsCONF-
dc.citation.beginningpage215-
dc.citation.endingpage220-
dc.citation.publicationnameESTC 2006 - 1st Electronics Systemintegration Technology Conference-
dc.identifier.conferencecountryGE-
dc.identifier.conferencelocationDresden, Saxony-
dc.embargo.liftdate9999-12-31-
dc.embargo.terms9999-12-31-
dc.contributor.localauthorKim, Joungho-
dc.contributor.nonIdAuthorRyu, C.-
dc.contributor.nonIdAuthorLee, J.-
dc.contributor.nonIdAuthorLee, H.-
dc.contributor.nonIdAuthorLee, K.-
dc.contributor.nonIdAuthorOh, T.-
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