Characterization and optimization of partially depleted SOI MOSFETs for high power RF switch applications
| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | Im, Donggu | ko |
| dc.contributor.author | Lee, Kwyro | ko |
| dc.date.accessioned | 2014-08-26T07:10:56Z | - |
| dc.date.available | 2014-08-26T07:10:56Z | - |
| dc.date.created | 2013-12-27 | - |
| dc.date.created | 2013-12-27 | - |
| dc.date.created | 2013-12-27 | - |
| dc.date.created | 2013-12-27 | - |
| dc.date.issued | 2013-12 | - |
| dc.identifier.citation | SOLID-STATE ELECTRONICS, v.90, pp.94 - 98 | - |
| dc.identifier.issn | 0038-1101 | - |
| dc.identifier.uri | http://hdl.handle.net/10203/187015 | - |
| dc.description.abstract | Power handling capability is the most stringent specification for an RF switch. The dominant reason to limit the power handling capability is undesirable channel formation (leakage current) on off-state FEETs in the event of large signal input. To characterize leakage current and find the correlation between DC I-V measurement and RFP1 dB measurement, a new DC characterization method (Float FET I-V characterization method) reflecting RF switch operation is proposed. Based on the proposed Float FET I-V method, an experimental study on optimum dc bias point, MOSFET device design, and stacked-FETs device design is performed in order to achieve maximum power handling capability of the RF switch. In addition, compared to RF measurement tests that take a long time, the proposed characterization method rapidly evaluates the various off-state MOS-FET leakage current mechanisms affecting the power handling capability of the RF switch. (C) 2013 Elsevier Ltd. All rights reserved. | - |
| dc.language | English | - |
| dc.publisher | PERGAMON-ELSEVIER SCIENCE LTD | - |
| dc.title | Characterization and optimization of partially depleted SOI MOSFETs for high power RF switch applications | - |
| dc.type | Article | - |
| dc.identifier.wosid | 000327676800016 | - |
| dc.identifier.scopusid | 2-s2.0-84887499382 | - |
| dc.type.rims | ART | - |
| dc.citation.volume | 90 | - |
| dc.citation.beginningpage | 94 | - |
| dc.citation.endingpage | 98 | - |
| dc.citation.publicationname | SOLID-STATE ELECTRONICS | - |
| dc.identifier.doi | 10.1016/j.sse.2013.02.046 | - |
| dc.contributor.localauthor | Lee, Kwyro | - |
| dc.contributor.nonIdAuthor | Im, Donggu | - |
| dc.type.journalArticle | Article; Proceedings Paper | - |
| dc.subject.keywordAuthor | Gate induced drain leakage (GIDL) | - |
| dc.subject.keywordAuthor | Power handling capability | - |
| dc.subject.keywordAuthor | RF switch | - |
| dc.subject.keywordAuthor | Silicon-on-Insulator (SOI) CMOS | - |
| dc.subject.keywordAuthor | Source-drain punch through | - |
| dc.subject.keywordAuthor | Stacked transistors | - |
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