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College of Engineering(공과대학)School of Electrical Engineering(전기및전자공학부)EE-Conference Papers(학술회의논문)

Jitter suppressed on-chip clock distribution using package plane cavity resonance

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dc.contributor.authorLee, W.ko
dc.contributor.authorRyu, C.ko
dc.contributor.authorPark, J.ko
dc.contributor.authorKim, Jounghoko
dc.date.accessioned2010-05-31T08:51:14Z-
dc.date.available2010-05-31T08:51:14Z-
dc.date.created2012-02-06-
dc.date.created2012-02-06-
dc.date.issued2008-05-19-
dc.identifier.citation2008 Asia-Pacific Symposium on Electromagnetic Compatibility and 19th International Zurich Symposium on Electromagnetic Compatibility, APEMC 2008, pp.427 - 430-
dc.identifier.urihttp://hdl.handle.net/10203/18681-
dc.languageEnglish-
dc.language.isoen_USen
dc.publisherIEEE-
dc.titleJitter suppressed on-chip clock distribution using package plane cavity resonance-
dc.typeConference-
dc.identifier.wosid000258515300108-
dc.identifier.scopusid2-s2.0-51749092886-
dc.type.rimsCONF-
dc.citation.beginningpage427-
dc.citation.endingpage430-
dc.citation.publicationname2008 Asia-Pacific Symposium on Electromagnetic Compatibility and 19th International Zurich Symposium on Electromagnetic Compatibility, APEMC 2008-
dc.identifier.conferencecountrySI-
dc.identifier.conferencelocationSuntec-
dc.embargo.liftdate9999-12-31-
dc.embargo.terms9999-12-31-
dc.contributor.localauthorKim, Joungho-
dc.contributor.nonIdAuthorLee, W.-
dc.contributor.nonIdAuthorRyu, C.-
dc.contributor.nonIdAuthorPark, J.-
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