DC Field | Value | Language |
---|---|---|
dc.contributor.author | Han, JH | ko |
dc.contributor.author | Park, In-Cheol | ko |
dc.date.accessioned | 2010-05-17T02:21:49Z | - |
dc.date.available | 2010-05-17T02:21:49Z | - |
dc.date.created | 2012-02-06 | - |
dc.date.created | 2012-02-06 | - |
dc.date.issued | 2008-05 | - |
dc.identifier.citation | IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, v.27, no.5, pp.958 - 962 | - |
dc.identifier.issn | 0278-0070 | - |
dc.identifier.uri | http://hdl.handle.net/10203/18363 | - |
dc.description.abstract | To reduce the hardware complexity of finite-impulse response (FIR) digital filters, this paper proposes a new filter synthesis algorithm. Considering multiple adder graphs for a coefficient, the proposed algorithm selects an adder graph that can be maximally sharable with the remaining coefficients, whereas previous dependence-graph algorithms consider only one adder graph when implementing a coefficient. In addition, an addition reordering technique is proposed to derive multiple adder graphs from a seed adder graph generated by using previous dependence-graph algorithms. Experimental results show that the proposed algorithm reduces the hardware cost of FIR filters by 22% and 3.4%, on average, compared to the Hartley and n-dimensional reduced adder graph hybrid algorithms, respectively. | - |
dc.language | English | - |
dc.language.iso | en_US | en |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.subject | DIGITAL-FILTERS | - |
dc.subject | ELIMINATION | - |
dc.subject | ALGORITHM | - |
dc.title | FIR filter synthesis considering multiple adder graphs for a coefficient | - |
dc.type | Article | - |
dc.identifier.wosid | 000255222600015 | - |
dc.identifier.scopusid | 2-s2.0-42649145082 | - |
dc.type.rims | ART | - |
dc.citation.volume | 27 | - |
dc.citation.issue | 5 | - |
dc.citation.beginningpage | 958 | - |
dc.citation.endingpage | 962 | - |
dc.citation.publicationname | IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS | - |
dc.identifier.doi | 10.1109/TCAD.2008.917581 | - |
dc.embargo.liftdate | 9999-12-31 | - |
dc.embargo.terms | 9999-12-31 | - |
dc.contributor.localauthor | Park, In-Cheol | - |
dc.contributor.nonIdAuthor | Han, JH | - |
dc.type.journalArticle | Article | - |
dc.subject.keywordAuthor | digital filter | - |
dc.subject.keywordAuthor | filter optimization | - |
dc.subject.keywordAuthor | finite-impulse response (FIR) filter synthesis | - |
dc.subject.keywordAuthor | multiplier block | - |
dc.subject.keywordPlus | DIGITAL-FILTERS | - |
dc.subject.keywordPlus | ELIMINATION | - |
dc.subject.keywordPlus | ALGORITHM | - |
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