A 9b, 1.12ps Resolution 2.5b/Stage Pipelined Time-to-Digital Converter in 65nm CMOS Using Time-Register
- Publisher
- IEEE
- Issue Date
- 2013-06-13
- Language
- English
- Citation
2013 IEEE Symposia on VLSI Technology and Circuits, pp.136 - 137
- Appears in Collection
- EE-Conference Papers(학술회의논문)
- Files in This Item
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