DC Field | Value | Language |
---|---|---|
dc.contributor.advisor | James Robert Morrison | - |
dc.contributor.advisor | 제임스모리슨 | - |
dc.contributor.author | Jin, Hong-Yue | - |
dc.contributor.author | 김홍월 | - |
dc.date.accessioned | 2013-09-12T05:57:03Z | - |
dc.date.available | 2013-09-12T05:57:03Z | - |
dc.date.issued | 2013 | - |
dc.identifier.uri | http://library.kaist.ac.kr/search/detail/view.do?bibCtrlNo=515043&flag=dissertation | - |
dc.identifier.uri | http://hdl.handle.net/10203/182465 | - |
dc.description | 학위논문(석사) - 한국과학기술원 : 산업및시스템공학과, 2013.2, [ v, 39 p. ] | - |
dc.description.abstract | Scheduling cluster tools is an important task in semiconductor wafer fabrication. An important issue is to determine when and how to schedule robot actions so that maximum throughput is achieved while maintaining good wafer quality. Since excessive wafer delays in process chambers may deteriorate wafer quality, wafer delays should be controlled within an acceptable range, or more preferably, should be minimized. Previous research focused on minimizing the cycle time, assuming the system is in steady state. However, the recent trend is to produce small amount of customized wafers, and the size of wafers is expected to grow from 300mm to 450mm. As a result, the transient period increases, which makes the steady state analysis less precise. For these reasons, this paper addresses the problem of non-cyclic scheduling with wafer delay constraints. To solve this problem, we first assumed that the robot sequence is given and developed a multistage linear programming (LP) model which consists of two LPs. The first LP model tries to minimize the total makespan while meeting the wafer delay constraints and the second LP tries to minimize the total wafer delay based on the result of the first LP. Then, we developed a branch & bound algorithm to find the optimal robot sequence with minimum wafer delay. First, we applied the dynamic programming approach introduced in the literature to find the lower bound of total makespan, and then we proposed an algorithm to find a tight upper bound. Finally, we modeled a LP model to check the feasibility of each branch. Applying the three mechanisms of lower bound, upper bound and feasibility check, fruitless nodes are eliminated at an early stage. Consequently, the computational efficiency increased substantially, which helped one solve problems that were not solvable otherwise. The simulation result shows that when the number of process modules grows to more than 5, the algorithm may fail to get the optimal solution due to computation... | eng |
dc.language | eng | - |
dc.publisher | 한국과학기술원 | - |
dc.subject | cluster tool | - |
dc.subject | non-cyclic scheduling | - |
dc.subject | wafer delay constraint | - |
dc.subject | linear programming | - |
dc.subject | 클러스터 툴 | - |
dc.subject | 비주기적 스케줄링 | - |
dc.subject | 웨이퍼 지연 조건 | - |
dc.subject | 선형계획법 | - |
dc.subject | 분기 한정법 | - |
dc.subject | branch and bound | - |
dc.title | Non-cyclic scheduling of single-armed cluster tools with wafer delay constraints | - |
dc.title.alternative | 비주기적 상태에서 웨이퍼 지연 제약을 가진 한팔 클러스터 툴의 스케줄링 | - |
dc.type | Thesis(Master) | - |
dc.identifier.CNRN | 515043/325007 | - |
dc.description.department | 한국과학기술원 : 산업및시스템공학과, | - |
dc.identifier.uid | 020114249 | - |
dc.contributor.localauthor | James Robert Morrison | - |
dc.contributor.localauthor | 제임스모리슨 | - |
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