DC Field | Value | Language |
---|---|---|
dc.contributor.advisor | Cho, Gyu-Seong | - |
dc.contributor.advisor | 조규성 | - |
dc.contributor.author | Lee, Dae-Hee | - |
dc.contributor.author | 이대희 | - |
dc.date.accessioned | 2013-09-12T04:55:50Z | - |
dc.date.available | 2013-09-12T04:55:50Z | - |
dc.date.issued | 2012 | - |
dc.identifier.uri | http://library.kaist.ac.kr/search/detail/view.do?bibCtrlNo=509430&flag=dissertation | - |
dc.identifier.uri | http://hdl.handle.net/10203/182245 | - |
dc.description | 학위논문(석사) - 한국과학기술원 : 원자력및양자공학과, 2012.8, [ iv, 53 p. ] | - |
dc.description.abstract | With the development of semiconductor technology, film-based radiography has been replaced by digital radiography which is made by semiconductor sensor. Digital radiography provides not only easy storing, searching, and sharing the radiographic image but also image processing using computers. There are a lot of applications like a chest, an oral, CT, mammography X-ray radiographic, and industrial NDT in digital radiography. Industrial NDT uses CCD, a-Si, and CMOS process in the digital radiography field. The image sensor using CMOS process in industrial NDT is mostly used as CMOS process has been developed. Industrial NDT needs a total inspection to test whether all products are wrong or not. The speed of total inspection is limited by not the speed of pixel operation but ADC conversion time with increase of the resolution of image. The commercial industrial NDT makes use of a Pipe-line ADC and SAR ADC mostly. These type of ADC are applied as chip-level ADC due to large layout area. But the design hardness is directly proportional to a square of increased pixel numbers as industrial NDT needs higher and higher resolution. In the other hand, integration ADC is applied for column-level ADC so that required conversion speed is directly proportional to increased pixel numbers. In this thesis, 2 times faster conversion speed than basic integration ADC is implemented by using complementary dual-slope signal. And the use of complementary dual-slope signal makes wide-input range of ADC possible so that we proposed high frame-rate and wide-input ADC. We designed 12 bit resolution and 25 KS/s CDS-ADC and experimented a static and dynamic test to get specification of the designed CDS-ADC. We derived that maximum DNL was 0.43 LSB, INL was 0.78 LSB, ENOB was 9.18 bit, and FoM was 0.003 pJ/conversion. Lastly, We anticipate that CDS-ADC will be faster 4 times, 8 times even 16 times faster as it uses more complementary dual-slope signal and improvement of found problem. | eng |
dc.language | eng | - |
dc.publisher | 한국과학기술원 | - |
dc.subject | Industrial NDT | - |
dc.subject | Integration ADC | - |
dc.subject | High frame-rate | - |
dc.subject | Wide-input range | - |
dc.subject | 산업용 비파괴 검사 | - |
dc.subject | 적분형 ADC | - |
dc.subject | 빠른 프레임 | - |
dc.subject | 넓은 입력 범위 | - |
dc.subject | CMOS 영상 센서 | - |
dc.subject | CMOS image sensor | - |
dc.title | A design of the high frame-rate and wide-input range ADC using complementary dual-slope for industrial NDT | - |
dc.title.alternative | 비파괴 검사에 쓰이는 빠른 프레임과 넓은 입력 범위를 가지는 상보적 램프 신호로 구현된 ADC | - |
dc.type | Thesis(Master) | - |
dc.identifier.CNRN | 509430/325007 | - |
dc.description.department | 한국과학기술원 : 원자력및양자공학과, | - |
dc.identifier.uid | 020104379 | - |
dc.contributor.localauthor | Cho, Gyu-Seong | - |
dc.contributor.localauthor | 조규성 | - |
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